Rom Correction Operation - Panasonic MN103S User Manual

6.3 ROM Correction Operation

ROM correction is designed to supply the microcontroller core (CPU, DMAC) with corrected data by replacing
part of data - data read from internal ROM as a result of access by the microcontroller core (CPU, DMAC) - with
the correction data stored in a ROM correction data register, thus allowing temporary correction of programs and
data stored in internal ROM.
6.3.1 ROM Correction Operation
ROM Correction Operation
Whether internal ROM access is made within the address range subject to correction (8 bytes or less from the
ROM correction address RCnAD) is detected by comparison between the address at which the microcontroller
core accesses internal ROM and the ROM correction address specified in the ROM correction address register
(RCRnAR). In the event of detection of access to an address subject to ROM correction, the data read from the
ROM is replaced with the correction data set in a ROM correction data register (RCRnDR). This ROM correction
function comes equipped with 4 channels, each of which can correct 8 bytes of data from a desired address in the
internal ROM. Each channel has a ROM correction address register (RCRnAR) and ROM correction data register
(RCRnDR) respectively to store correction address and correction data.
Instruction
Instruction
Instruction
Instruction
NG instruction
NG instruction
NG instruction
NG instruction
NG instruction
NG instruction
NG instruction
NG instruction
Instruction
Instruction
Instruction
ROM
RCRnAR
Correction address
Figure:6.3.1 ROM Correction Operation
RCRnDR
Correction instruction
Correction instruction
Correction instruction
Correction instruction
Correction instruction
Correction instruction
Correction instruction
Correction instruction
ROM Correction Operation
Chapter 6
ROM Correction
VI - 11