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Section
XIII-3
Figure
13.1.1
XIII-4
Note
XIII-7
bp7
bp5
Note
XIII-11
Activati
on
Factors
for
Commu-
nication
Transmi
ssion
Data
Buffer
XIII
Recepti
-12
on Data
Buffer
Note 4
Setting
Start
Condition
XIII
Table
-15
13.3.4
XIII
Note
-16
Recepti
on Buffer
Empty
Flag
Operation
Transmi
ssion
Buffer
Empty
Flag
Operation
Record of Changes - 5
Definition
Previous Edition (Ver.1.1)
Change
Start condition
detection circuit
M
U
X
M
Add
-
Change
SC2IOM
Serial data input selection
Change
SC2SBIS
Add
-
Change
However, the external clock should be fed
after more than 2.5 transfer clock ...
Change
... into the internal shift register. ... into the
internal shift register. 2.5 transfer clock cycles
...
Change
... the received data by the internal shift regis-
ter. After the communication complete inter-
rupt SC2TIRQ is generated, data stored in the
internal shift register ...
Change
Wait more than 2.5 transfer clocks for ...
Change
... before change the start condition edge.
Change
At slave
[1-bit data length of external clock x
1/2]+[Internal clock cycle x (1 to 2)]
Add
-
Change
... stored from the internal shift register into
SC2RB. ...
Change
... is generated after data is load into the inter-
nal shift register), ...
Read/Write
SWAP MSB<->LSB
SC2DIR
Reception
Transmission
buffer
buffer
SC2TB
SC2RB
SC2STE SC2CMD
Reception
Transmission
shift register
shift register
Start condition
Transmission
generation circuit
control circuit
SC2RDB
SC2TRB
0: "1" input
1: Serial input
New Edition (Ver.1.2)
Read/Write
SWAP MSB<->LSB
Reception
Transmission
data buffer
data buffer
Start condition
SC2TB
SC2RB
detection circuit
Reception
Transmission
shift register
shift register
SC2TRB
M
SC2RDB
U
X
M
Whe changing the setting value ... registers
are set to "0".)
SC2IOM
Serial data input pin selection
SC2SBIS
Whe changing the setting value ... registers
are set to "0".)
However, the external clock should be fed after
more than 3.5 transfer clock ...
... into the transmission shift register. ... into
the internal shift register. 3.5 transfer clock
cycles ...
... the received data by the reception shift reg-
ister. After the communication complete inter-
rupt SC2TIRQ is generated, data stored in the
reception shift register ...
Wait more than 3.5 transfer clocks for ...
... before change the start condition edge.
Then, select "without start condition" when
performing transmission and reception at the
same time. It may not be operated properly.
At slave
[1-bit data length of external clock x
1/2]+[Internal clock cycle x (1/2 to 3/2)]
In using synchronous serial interface, ...
GI5IR0 is not generated.
... stored from the reception shift register into
SC2RB. ...
... is generated after data is load into the trans-
mission shift register), ...
SC2DIR
SC2STE SC2CMD
S
Transmission
Start condition
generation circuit
control circuit
0: "1" input fix
1: Serial data input
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