Panasonic MN103S User Manual page 384

Chapter 13
Serial Interface 2
Reception Data Buffer
The reception data buffer SC2RB is a spare buffer that pushes the received data by the reception shift register.
After the communication complete interrupt SC2TIRQ is generated, data stored in the reception shift register is
automatically stored in the reception data buffer SC2RB. SC2RB can store data up to 1 byte. SC2RB is rewritten
in every time when communication is completed; so, read out data of SC2RB until the next reception is com-
pleted. The reception data buffer empty flag SC2RB is set to "1" after SC2RB is generated. SC2RB is cleared to
"0" when SC2RB is read out.
If a start condition is fed and activation restarts during communication, the transmission data
is invalid. Set the transmission data to SC2TB again to retransmit data.
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SC2RB is rewritten every time when communication is completed. Data of SC2RB should be
read out until the next reception is completed for continuous communication.
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Setting Transfer Bit
The transfer bit count can be set from 1 bit to 8 bits. Set the SC2LNG2 to 0 flag of the SC2CTR0 register (at reset:
111) . The SC2LNG2 to 0 flags retain the previous value until a new value is set.
The SBT2 pin is masked inside serial interface to prevent operating errors by noise, except
during communication. At slave communication, set data to SC2TB or input a start condition
before feeding a clock to the SBT2 pin.
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Wait more than 3.5 transfer clocks for feeding the external clock after the data set to SC2TB.
Otherwise, normal communication is not guaranteed.
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Setting Start Condition
Enable or disable of start condition can be selected with the SC2STE flag of the SC2CTR0 register.
Start condition is detected when the SC2CE1 flag of the SC2CTR0 register is set to "0" and data line SBI2 pin (3
channels) or SBO2 pin (2 channels) changes from "H" to "L" while the clock line (SBT2 pin) is "H". It is also
detected when the SC2CE1 flag of the SC2CTR0 register is set to "1", and data line SBI2 pin (3 channels) or
SBO2 pin (2 channels) changes from "H" to "L" while the clock line (SBT2 pin) is "L".
Set the SC2SBOS flag and SC2SBIS flag of the SC2CTR1 register to "0" before change the start condition edge.
Then, select "without start condition" when performing transmission and reception at the same time.
It may not be operated properly.
Setting First Transfer Bit
The SC2DIR flag of the SC2CTR0 register sets the first bit at transfer. LSB or MSB first can be selected.
XIII - 12 Operation