Panasonic MN103S User Manual page 213

Timer 5 Mode Register (TM5MD: 0x0000A1A1) [8-bit Access Register]
bp 7 6
Flag TM5 TM5
CNE LDE
At reset 0 0
Access R/W R/W
bp Flag Description
Timer operation enable
7 TM5CNE
Timer initialization
6 TM5LDE
5-3 - -
Count clock source selection
TM5CK2
2-0 TM5CK1
TM5CK0
5 4 3 2
- - - TM5 TM5
CK2 CK1
0 0 0 0
R R R R/W R/W
1 0
TM5
CK0
0 0
R/W
Set condition
0: Operation disabled
1: Operation enabled
0: Normal operation
1: Initialization
TM5BR value is loaded into TM5BC. Timer output 5 is set to "L" level.
-
000: IOCLK
001: IOCLK/8
010: IOCLK/32
011: Cascading with timer 4
100: Timer 4 underflow[
101: Setting prohibited
110: Timer 6 underflow
111: TM5IO pin input (rising edge)
When 1/8 IOCLK or 1/32 IOCLK are used, the prescaler control regis-
ter (TM47PSC) should be set.
Chapter 8
8-bit Timer
Control Registers VIII - 23