Panasonic MN103S User Manual page 210

Chapter 8
8-bit Timer
Timer 2 Mode Register (TM2MD: 0x0000A184) [8-bit Access Register]
bp 7
Flag TM2
CNE
At reset 0
Access R/W
bp Flag
7 TM2CNE
6 TM2LDE
5-3 -
TM2CK2
2-0 TM2CK1
TM2CK0
When the count clock source is set to IOCLK/128, set the TM2IN flag of the external prescaler control
register TMEXPSC8 to "1" and the EXPSCNE flag to " 1".
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VIII - 20 Control Registers
6 5 4 3
TM2 - - -
LDE
0 0 0 0
R/W R R R
Description
Timer operation enable
Timer initialization
-
Count clock source selection
2 1 0
TM2 TM2 TM2
CK2 CK1 CK0
0 0 0
R/W R/W R/W
Set condition
0: Operation disabled
1: Operation enabled
0: Normal operation
1: Initialization
TM2BR value is loaded into TM2BC. Timer output 2 is set to "L" level.
-
000: IOCLK
001: IOCLK/8
010: IOCLK/32
011: Cascading with timer 1
100: Timer 0 underflow
101: Timer 1 underflow
110: Setting prohibited
111: TM2IO pin input (rising edge), IOCLK/128
When 1/8 IOCLK and 1/32 IOCLK are used, the prescaler control reg-
ister (TM03PSC) should be set.