Panasonic MN103S User Manual page 510

Chapter 16
Appendix
MACHU (unsigned halfword data multiply and accumulate instruction: register to register)
[Instruction format (macro name)]
MACHU Dm, Dn
[Assembler mnemonic]
udf31 Dm, Dn
[Operation]
This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in
the extension arithmetic unit.
The instruction multiplies the content of Dm (unsigned 16-bit integer : multiplicand) by the content of Dn
(unsigned 16-bit integer: multiplier), adds this product to the 64-bit accumulative sum whose high-order 32 bits
and low-order 32 bits are stored respectively in the multiply and accumulate registers MCRH and MCRL and
stores high-order 32 bits and low-order 32 bits of the 64-bit result respectively in the multiply and accumulate
registers MCRH and MCRL.
The register outputs a multiply and accumulate overflow detection flag "1" to the register MCVF if the 0
accumulative sum data overflows beyond 64 bits during addition of the product and the accumulative sum.
[Flag changes]
Flag Change
V -
C -
N -
Z -
[Note for programming]
An instruction other than extension instructions that requires 1 or more cycles must be inserted between this
instruction and a next extension instruction.
XVI - 58 Extension Instruction Specification
Condition