Panasonic MN103S User Manual page 252

Chapter 9
16-bit Timer
Table:9.2.3 Updated Timing of Compare/Capture Register (At Double Buffer)
When initializing a timer (when the
TMLDE flag of the TMnMD register is set
to "1")
Count clock up (down)
TMnBC overflow
TMnBC underflow
Counting up (down) when the TMnBC
and the TMnCA match
Counting up (down) when the TMnBC
and the TMnCB match
At the TMnCA capture
At the TMnCB capture
TMnCBUFF: compare register buffer
2. When the compare/capture register is set to capture operation
The value of the TMnBC is captured into TMnCA (TMnCB) by inputting the edge selected to the TMAIN
(TMBIN) pin; and, the interrupt request (TMAIRQ, TMBIRQ) is generated.
IX - 16 Control registers
TMLCE flag (TMnMD)=0
TMnCA←TMnCBUFF *1
TMnCB←TMnCBUFF
-
TMnCA←TMnCBUFF
TMnCB←TMnCBUFF
TMnCA←TMnCBUFF
TMnCB←TMnCBUFF
-
-
-
-
TMLCE flag (TMnMD)=1
TMnCA←TMnCBUFF
TMnCB←TMnCBUFF
-
-
-
TMnCA←TMnCBUFF
TMnCB←TMnCBUFF *2
-
TMnBC←TMnCBUFF *3
-
*1 TMnCBUFF: compare register buffer
*2 When the TMnCA is set to the compare register
*3 When the TMnCA is set to the capture register