Panasonic MN103S User Manual page 79

Setup Procedure
(1) Set the multiplication ratio
PCNT (0x0000AFF2)
bp5: PLLSEL=0
bp3: PLLON=0
bp1: CKSEL1=0
bp0: CKSEL0=1
(2) Wait PLL lock time
over 200 µs
(3) Select PLL output
PCNT (0x0000AFF2)
bp5: PLLSEL=1
bp3: PLLON=0
bp1: CKSEL1=0
bp0: CKSEL0=1
(4) Set the frequency of MCLK and IOCLK
CKCTR (0x00008280)
bp5: IOCLK1=1
bp3: IOCLK0=1
bp1: MCK1=1
bp0: MCK0=1
When the CPU clock (MCLK) is 40 MHz or over, change an access to the internal ROM to 3
cycle access (ROMMC[1:0]=10) by the internal ROM access control register (ROMCTR)
before the PLLSEL flag of the PLL control register (PCNT) is switched "0" to "1".
..
The operation that is set to 2 cycle access is not guranteed.
..
When the PLLON and CKSEL [1:0] flags of the PCNT register are changed, reset the PLLSEL flag to
"0" before the change and set to "1" after waiting over 200 µs.
.. ..
(1) Set the PLL multiplication ratio to 6 by the CKSEL 1 and
CKSEL0 of the PLL control register (PCNT).
Note: Set the frequency ( oscillation frequceny
multiplication ratio) to 40MHz≤PLLOUT≤60MHz
µ
(2) Wait 200 s by the execution of the loop program etc.
(3) Set the PLLSEL of the PLL control register (PCNT) to "1"
to select the PLL output to the internal clock.
Note: Do not change the values of PLLON, CKSEL1
and CKSEL0.
(4) Set the cycle division of MCLK and IOCLK. This setting
is not necessary when MCLK=PLLOUT and IOCLK=1/
2PLLOUT.
Description
Operation
Chapter 3
Clock Generator
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