Panasonic MN103S User Manual page 492

Chapter 16
Appendix
The following shows symbols used in flag change tables:
- : Flag unchanged
+ : Flag changed
* : Undefined
0 : Reset
1 : Set
Low-order 4 bits (V, C, N, Z) of PSW are collectively called "flags".
.. ..
Extension arithmetic unit register set
Each of the extension arithmetic units has the following dedicated registers to store high-speed multiply and
multiply and accumulate results:
Multiply register (one 32-bit register)
This register is provided for high-speed multiply instruction and stores high-order 32 bits of multiply result that is
64 bits long when multiply instruction is used.
Multiply and accumulate register (higher) (one 32-bit register)
This register is provided for multiply and accumulate instructions and stores high-order 32 bits of multiply and
accumulate result that is 64 bits long when multiply and accumulate instruction is used.
Multiply and accumulate register (lower) (one 32-bit register)
This register is provided for multiply and accumulate instruction and stores low-order 32 bits of multiply and
accumulate result that is 64 bits long when multiply and accumulate instruction is used.
Multiply and accumulate overflow detection flag register (one 1-bit register)
This register is set when an overflow occurs as a result of execution of multiply and accumulate instruction and is
not cleared until the next CLRMAC or PUTCX instruction is executed.
XVI - 40 Extension Instruction Specification
Multiply Register
Multiply & Accumulate
Register(Higher)
Multiply & Accumulate
Register(Lower)
Multiply & Accumulate
Overflow Detect Flag Register
Figure:16.4.2 Extension Arithmetic Unit Register Set
31
MDRQ
31
MCRH
31
MCRL
0
0
0
0
MCVF