Panasonic MN103S User Manual page 360

Chapter 12
Serial interface 0 and 1
Transmission Timing
Clock
(SBTn pin)
Output pin
(SBOn pin)
Transfer bit
counter
SC2TBSY
(Data set in SBnTB)
Interrupt(SCnTIRQ)
Reception Timing
Clock
(SBTn pin)
Input pin
(SBIn pin)
Transfer bit
counter
SCAnRBSY
Interrupt
(SCnRIRQ)
XII - 14 Operation
At master
Tmax=3.5T
T
0
Figure:12.3.3 Transmission Timing (At Falling Edge)
At master
Tmax=3.5T T
0 1
Figure:12.3.4 Reception Timing (At Rising Edge)
1 2 3 4
2 3 4 5
5 6 7
6 7