Cautions For Programming - Panasonic MN103S User Manual

Setup Procedure
(6) Enable all maskable interrupts.
PSW
bp11: IE = 1
5.3.4

Cautions for Programming

External Interrupt Request Signal
Maintain the external pin of the interrupt request signal for a minimum of 3 cycles of a system clock (MCLK).
The level detection can not be achieved if the signal is not maintained for at least that long.
When the GnICR register is changed
Clear the IE flag of the PSW to "0" to change the GnICR.
Processing in Interrupt program
When the GnIR and GnID flags of the GnICR register are cleared and restored from the interrupt program, write
the instruction for the I/O bus access between the clear processing instruction (movhu etc., ) of the GnICR register
and the restore instruction to synchronize with the store buffer of the bus controller.
mov 0x0f:b,d0
movbu d0,(GnICR)
movhu (GnICR),d1
rti
When there is no instruction for the I/O bus access, the restore operation from the interrupt is not guaranteed.
When the restore instruction is written right after the clear processing instruction of the GnICR register, a mal-
function that the interrupt program is executed occurs.
mov 0x0f:b,d0
movbu d0,(GnICR)
rti
(6) Set the IE flag of PSW to "1" to enable maskable
d0=clear data
GnIR and GnID flags of the GnICR register
I/O bus access
Restore instruction
d0=clear data
Clear the GnIR and GnID flag of the GnICR register
Restore instruction
Description
interrupts.
Interrupt Controller
Interrupt Controller Operation
Chapter 5
V - 39