Pin Functions - Panasonic F77G User Manual

1-3-3

Pin Functions

Name No. I/O
VDD 7
VSS 10
OSC1 9 Input
OSC2 8 Output
XI 11 Input
XO 12 Output
NRST 14 I/O
P00 15 I/O
P01 16
P02 17
P03 18
P04 19
P05 20
P06 21
P10 22 I/O
P11 23
P12 24
P13 25
P14 26
Table 1-3-3 Pin Function Summary (1/6)
Function Other Function
Power supply pin
Clock input pin
Clock output pin
Clock input pin
Clock output pin
Reset pin P27
I/O port 0 SBO1A, TXD1A
SBI1A, RXD1A
SDA4B
SBT1A, SCL4B
SBO0A, TXD0A
SBI0A, RXD0A
SBT0A
BUZZER
I/O port 1 TCO0A, RMOUTA
TCIO0B, RMOUTB
TCO4A
TCIO4B
TCI07
Description
Supply 1.8 V to 3.6 V to VDD and 0 V to VSS.
Connect these oscillation pins to ceramic or
crystal oscillators for high-frequency clock
operation.
If the clock is an external input, connect it to OSC1
and leave OSC2 open. The chip will not operate
with an external clock when using either the
STOP or SLOW modes.
Connect these oscillation pins to ceramic
oscillators or crystal oscillators for low-frequency
clock operation.
If the clock is an external input, connect it to XI
and leave XO open. The chip will not operate with
an external clock when using the STOP mode. If
these pins are not used, connect XI to VSS and
leave XO open.
This pin resets the chip when power is turned on,
is allocated as P27 and contains an internal pull-
up resistor. Setting this pin low initializes the
internal state of the device. Thereafter, setting the
input to high releases the reset. The hardware
waits for the system clock to stabilize, then
processes the reset interrupt. Also, if ""0"" is
written to P27 and the reset is initiated by
software, a low level will be output. The output
has an n-channel open-drain configuration. If a
capacitor is to be inserted between NRST and
VDD, it is recommended that a discharge diode
be placed between NRST and VDD.
7-Bit CMOS tri-state I/O port.
Each bit can be set individually as either an input
or output by the P0DIR register. A pull-up resistor
for each bit can be selected individually by the
P0PLU register.
At reset, the input mode is selected and pull-up
resistors are disabled (high impedance output).
5-Bit CMOS tri-state I/O port.
Each bit can be set individually as either an input
or output by the P1DIR register. A pull-up resistor
for each bit can be selected individually by the
P1PLU register.
At reset, the input mode is selected and pull-up
resistors are disabled (high impedance output).
Pin Description
Chapter 1 Overview
I - 11