Epson S1C17W34 Technical Manual
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Epson S1C17W34 Technical Manual

Epson S1C17W34 Technical Manual

Cmos 16-bit single chip microcontroller
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17W34/W35/W36
Technical Manual
Rev. 1.2

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Summary of Contents for Epson S1C17W34

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17W34/W35/W36 Technical Manual Rev. 1.2...
  • Page 2 2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it.

  • Page 3: Notational Conventions And Symbols In This Manual

    PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17W34/W35/ W36. This document describes the functions of the IC, embedded peripheral circuit operations, and their con- trol methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.

  • Page 4: Table Of Contents

    3.2 CPU Core ........................3-2 3.2.1 CPU Registers ....................3-2 3.2.2 Instruction Set ....................3-2 3.2.3 Reading PSR ....................3-2 3.2.4 I/O Area Reserved for the S1C17 Core ............3-2 3.3 Debugger ........................3-2 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 5 6.2.4 CMOS Output and High Impedance State ............6-3 6.3 Clock Settings ......................... 6-3 6.3.1 PPORT Operating Clock ................... 6-3 6.3.2 Clock Supply in SLEEP Mode ................6-3 6.3.3 Clock Supply in DEBUG Mode ................. 6-3 6.4 Operations ........................6-3 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 6 9.3.2 Theoretical Regulation Function ............... 9-2 9.4 Operations ........................9-3 9.4.1 RTCA2 Control ....................9-3 9.4.2 Real-Time Clock Counter Operations ............... 9-4 9.4.3 Stopwatch Control .................... 9-5 9.4.4 Stopwatch Count-up Pattern ................9-5 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 7 11.3.4 Event Counter Clock ..................11-2 11.4 Operations ........................11-2 11.4.1 Initialization ....................11-2 11.4.2 Counter Underflow ..................11-3 11.4.3 Operations in Repeat Mode ................11-3 11.4.4 Operations in One-shot Mode ............... 11-3 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 8 13.2.3 Pin Functions in Master Mode and Slave Mode ..........13-3 13.2.4 Input Pin Pull-Up/Pull-Down Function ............13-3 13.3 Clock Settings ......................13-3 13.3.1 SPIA Operating Clock ..................13-3 13.3.2 Clock Supply in DEBUG Mode ..............13-4 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 9 15 16-bit PWM Timers (T16B) ..................15-1 15.1 Overview ........................15-1 15.2 Input/Output Pins ......................15-2 15.3 Clock Settings ......................15-3 15.3.1 T16B Operating Clock ................... 15-3 15.3.2 Clock Supply in SLEEP Mode ............... 15-3 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 10 17.3.1 REMC2 Operating Clock ................17-2 17.3.2 Clock Supply in SLEEP Mode ............... 17-2 17.3.3 Clock Supply in DEBUG Mode ..............17-2 17.4 Operations ........................17-2 17.4.1 Initialization ....................17-2 17.4.2 Data Transmission Procedures ..............17-3 Seiko Epson Corporation viii S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 11 LCD32B Power Control Register ..................... 18-26 LCD32B Display Control Register ................... 18-27 LCD32B COM Pin Control Registers 0 and 1 ................. 18-28 LCD32B Interrupt Flag Register ....................18-29 LCD32B Interrupt Enable Register ..................18-29 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 12 21.1 Overview ........................21-1 21.2 Output Pin and External Connections ................. 21-1 21.2.1 Output Pin ...................... 21-1 21.2.2 External Connections ..................21-2 21.3 Operations ........................21-2 21.3.1 Reference Voltage Setting ................21-2 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 13 C (I2C) ..................AP-A-16 0x5000–0x501a 16-bit PWM Timer (T16B) Ch.0 ..........AP-A-17 0x5040–0x505a 16-bit PWM Timer (T16B) Ch.1 ..........AP-A-18 0x5080–0x509a 16-bit PWM Timer (T16B) Ch.2 ..........AP-A-20 0x5200–0x520e UART (UART2) Ch.1 ..............AP-A-21 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 14 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Revision History Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 15: Overview

    1 OVERVIEW 1 Overview The S1C17W34/W35/W36 is a 16-bit MCU that features low-voltage operation from 1.2 V even though Flash memory is included. The embedded high-efficiency DC-DC converter generates the constant-voltage to drive the IC with lower power consumption than 4-bit MCUs. This IC includes a real-time clock, a stopwatch, an LCD driv- er, a temperature sensor, an A/D converter, and a PWM timer capable of being used to generate drive waveforms for a motor driver as well as a high-performance 16-bit CPU.
  • Page 16 LCD driver 2.5 to 3.6 V operating voltage for super economy mode 2.5 to 3.6 V Operating temperature Operating temperature range -40 to 85 °C Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 17: Block Diagram

    12-bit A/D CAP20–21 #ADTRG0 EXCL00–01 converter ADIN00–06 EXCL10–11 (ADC12A) (ADIN07) 1 Ch. EXCL20–21 VREFA0 UART Temperature USIN0–1 (UART2) sensor USOUT0–1 2 Ch. & Reference voltage generator (TSRVR) Figure 1.2.1 S1C17W34/W35/W36 Block Diagram Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 18: Pins

    COM11 SEG44 SEG44 COM12 COM12 SEG43 SEG43 COM13 COM13 SEG42 SEG42 COM14 COM14 COM15 COM15 SEG0 SEG0/COM16 SEG1 SEG1/COM17 SEG2 SEG2/COM18 SEG3 SEG3/COM19 SEG4 SEG4/COM20 Figure 1.3.1.1 S1C17W34/W35/W36 Pin Configuration Diagram (QFP21-176PIN) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 19: Pad Configuration Diagram (Chip)

    SEG0/COM16 SEG1 SEG1/COM17 SEG2 SEG2/COM18 SEG3 SEG3/COM19 SEG4 SEG4/COM20 4.100 mm Figure 1.3.2.1 S1C17W34/W35/W36 Pad Configuration Diagram (Chip) Pad opening: X = 68 µm, Y = 68 µm Chip thickness: 400 µm Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 20 1 OVERVIEW Table 1.3.2.1 S1C17W34/W35/W36 Pad Coordinates X µm Y µm X µm Y µm X µm Y µm X µm Y µm -1,725.0 -1,950.0 1,960.0 -1,850.0 1,740.0 1,950.0 -1,960.0 1,724.5 -1,645.0 -1,950.0 1,960.0 -1,770.0 1,660.0 1,950.0 -1,960.0 1,644.5 -1,565.0 -1,950.0 1,960.0 -1,690.0...

  • Page 21: Pin Descriptions

    User-selected I/O (universal port multiplexer) VREFA0 12-bit A/D converter Ch.0 reference voltage input Hi-Z – I/O port UPMUX User-selected I/O (universal port multiplexer) ADIN00 12-bit A/D converter Ch.0 analog signal input 0 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 22 User-selected I/O (universal port multiplexer) Hi-Z – I/O port UPMUX User-selected I/O (universal port multiplexer) – Hi-Z I/O port UPMUX User-selected I/O (universal port multiplexer) Hi-Z – I/O port UPMUX User-selected I/O (universal port multiplexer) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 23 SEG70 Hi-Z – LCD segment output COM25 LCD common output SEG71 SEG71 Hi-Z – LCD segment output COM24 LCD common output SEG72 SEG72 Hi-Z – LCD segment output COM23 LCD common output Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 24 = 0, 1, 2 T16B Ch.n PWM output/capture input 0 (T16B) TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 25: Power Supply, Reset, And Clocks

    Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Dia- gram” chapter, respectively. Note: Be sure to avoid using the V and V pin outputs for driving external circuits. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 26: Operations

    PWGINTF.MODCMPIF bit to 1. 2. When a clock source other than OSC1 is started in economy mode The hardware switches to normal mode at the same time the clock source is started. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 27 (or economy mode). Do not perform heavy- load operations, such as starting a high-speed clock source, before the PWGINTF.MODC- MPIF bit is set to 1, as it may cause a malfunction. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 28: System Reset Controller (Src)

    The reset source refers to causes that request system initialization. The following shows the reset sources. #RESET pin Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 29: Initialization Conditions (Reset Groups)

    Watchdog timer reset #RESET pin Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 30: Clock Generator (Clg)

    EXOSCEN EXOSC EXOSC EXOSCCLK clock input circuit FOUTEN FOUT0 Peripheral circuit 1 FOUT Clock output CLKSRC[x:0] FOUT1 selector circuit CLKDIV[x:0] FOUTDIV[2:0] Peripheral circuit n Clock CLKSRC[x:0] selector CLKDIV[x:0] Figure 2.3.1.1 CLG Configuration Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 31: Input/Output Pins

    OSC1 oscillator circuit The OSC1 oscillator circuit is a high-precision and low-power oscillator circuit that uses a 32.768 kHz crystal resonator. Figure 2.3.3.2 shows the configuration of the OSC1 oscillator circuit. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 32: Osc3 Oscillator Circuit

    OSC3 and OSC4 pins may affect the oscillation frequency. • When the internal oscillator is selected, be sure to avoid using the pins to which OSC3 and OSC4 are assigned as input pins, as it may affect the oscillation frequency. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 33: Operations

    Figure 2.3.4.1 shows the relationship be- tween the oscillation start time and the oscillation stabilization waiting time. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 34 Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1B[1:0] setting gain INV1N[1:0] setting gain Oscillation waveform Startup boosting Normal operation operation Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used Seiko Epson Corporation 2-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 35 (Set oscillation inverter gain) Configure the following bits when using the internal oscillator: - CLGOSC3.OSC3FQ[2:0] bits (Select oscillation frequency) 6. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-11 (Rev. 1.2)

  • Page 36: System Clock Switching

    This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function. Seiko Epson Corporation 2-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 37 10 ms is required. When IOSCCLK is being used as the system clock or a peripheral circuit clock, do not use the auto-trimming function. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-13 (Rev. 1.2)

  • Page 38: Operating Mode

    RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation 2-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 39 CLGSCLK.CLKSRC[1:0] = 0x3 EXOSC HALT OSC3 OSC3 ∗ In RUN and HALT modes, the clock sources not used HALT as SYSCLK can be all disabled. Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-15 (Rev. 1.2)

  • Page 40: Interrupts

    Bit name Initial Reset Remarks PWGCTL 15–8 – 0x00 – – 7–3 – 0x00 – 2–0 PWGMOD[2:0] R/WP Bits 15–3 Reserved Bits 2–0 PWGMOD[2:0] These bits control the PWG2 operating mode. Seiko Epson Corporation 2-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 41: Pwg2 Timing Control Register

    0x00 – – 7–1 – 0x00 – MODCMPIE Bits 15–1 Reserved Bit 0 MODCMPIE These bits enable the PWG2 mode transition completion interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-17 (Rev. 1.2)

  • Page 42: Clg System Clock Control Register

    These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation 2-18 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 43: Clg Oscillation Control Register

    Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-19 (Rev. 1.2)

  • Page 44: Clg Iosc Control Register

    0. Bit 12 OSC1BUP This bit enables the oscillation startup control circuit in the OSC1 oscillator circuit. 1 (R/WP): Enable (Activate booster operation at startup.) 0 (R/WP): Disable Seiko Epson Corporation 2-20 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 45 These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit. Table 2.6.8 OSC1 Oscillation Stabilization Waiting Time Setting CLGOSC1.OSC1WT[1:0] bits Oscillation stabilization waiting time 65,536 clocks 16,384 clocks 4,096 clocks Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-21 (Rev. 1.2)

  • Page 46: Clg Osc3 Control Register

    These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit. Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting CLGOSC3.OSC3WT[2:0] bits Oscillation stabilization waiting time 65,536 clocks 16,384 clocks 4,096 clocks 1,024 clocks 256 clocks 64 clocks 16 clocks 4 clocks Seiko Epson Corporation 2-22 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 47: Clg Interrupt Flag Register

    Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized. CLG Interrupt Enable Register Register name Bit name Initial Reset Remarks CLGINTE 15–8 – 0x00 – – – – (reserved) OSC1STPIE IOSCTEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-23 (Rev. 1.2)

  • Page 48: Clg Fout Control Register N

    1/256 1/16 Reserved Reserved Reserved Reserved Note: When the CLGFOUTn.FOUTSRC[1:0] bits are set to 0x3, the FOUTn output will be stopped in SLEEP/HALT mode as SYSCLK is stopped. Bit 1 Reserved Seiko Epson Corporation 2-24 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 49: Clg Oscillation Frequency Trimming Register

    Be aware that the frequency characteristics may not be sat- isfied when these settings are altered. When altering these settings, always make sure that the relevant oscillator circuit is inactive. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 2-25 (Rev. 1.2)

  • Page 50: Cpu And Debugger

    3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...

  • Page 51: Cpu Core

    DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DE- BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in- struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 52: Resource Requirements And Debugging Tools

    For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 53: Flash Security Function

    The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit. Bit 0 PSRN The value (0 or 1) of the PSR N (negative) flag can be read out with this bit. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 54: Debug Ram Base Register

    – 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 55: Memory And Bus

    Bit width of the memory and peripheral circuits that can be accessed in one cycle • Access size: Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 56: Flash Memory

    The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 57: Flash Programming

    The embedded display data RAM is used to store display data for the LCD driver. Areas unused for display data in the display data RAM can be used as a general-purpose RAM. For specific information on the display data RAM, refer to “Display Data RAM” in the “LCD Driver” chapter. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 58: Peripheral Circuit Control Registers

    0x40e0 RTCSEC3 RTC Time Zone 3 Second/1Hz Register 0x40e2 RTCHUR3 RTC Time Zone 3 Hour/Minute Register 0x40e4 RTCMON3 RTC Time Zone 3 Month/Day Register 0x40e6 RTCYAR3 RTC Time Zone 3 Year/Week Register Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 59 P5 Port Interrupt Flag Register 0x4258 P5INTCTL P5 Port Interrupt Control Register 0x425a P5CHATEN P5 Port Chattering Filter Enable Register 0x42d0 PDDAT Pd Port Data Register 0x42d2 PDIOEN Pd Port Enable Register Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 60 T16B Ch.0 Max Counter Data Register 0x5006 T16B0TC T16B Ch.0 Timer Counter Data Register 0x5008 T16B0CS T16B Ch.0 Counter Status Register 0x500a T16B0INTF T16B Ch.0 Interrupt Flag Register 0x500c T16B0INTE T16B Ch.0 Interrupt Enable Register Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 61 REMC2 Clock Control Register 0x5322 REMDBCTL REMC2 Data Bit Counter Control Register 0x5324 REMDBCNT REMC2 Data Bit Counter Register 0x5326 REMAPLEN REMC2 Data Bit Active Pulse Length Register 0x5328 REMDBLEN REMC2 Data Bit Length Register Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 62 0x54b8 ADC12_0AD6D ADC12A Ch.0 Result Register 6 0x54ba ADC12_0AD7D ADC12A Ch.0 Result Register 7 Temperature sensor/reference 0x54c0 TSRVR0TCTL TSRVR Ch.0 Temperature Sensor Control Register voltage generator (TSRVR) 0x54c2 TSRVR0VCTL TSRVR Ch.0 Reference Voltage Generator Control Register Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 63: System-Protect Function

    FLASHC Flash Read Cycle Register Register name Bit name Initial Reset Remarks FLASHCWAIT 15–9 – 0x00 – – (reserved) R/WP Always set to 0. – 7–2 – 0x00 – 1–0 RDWAIT[1:0] R/WP Bits 15–2 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 64 FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 4.2 MHz (max.) 4.2 MHz (max.) 4.2 MHz (max.) 2.1 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation 4-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 65: Interrupt Controller (Itc)

    Address misaligned interrupt Memory access instruction – (0xfffc00) Debugging interrupt brk instruction, etc. 2 (0x02) TTBR + 0x08 Watchdog timer overflow 3 (0x03) TTBR + 0x0c Reserved for C compiler – – Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 66 • Sound buffer empty • Sound output completion 21 (0x15) TTBR + 0x54 IR remote controller interrupt • Compare AP • Compare DB 22 (0x16) TTBR + 0x58 LCD driver interrupt Frame Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 67: Vector Table Base Address (Ttbr)

    ITC even if the interrupt flag is set to 1. An interrupt request is also sent to the ITC if the status is changed to interrupt enabled when the interrupt flag is 1. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 68: Itc Interrupt Request Processing

    (0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 69: Interrupt Processing By The Cpu

    – 2–0 ILVy [2:0] Bits 15–11 Reserved Bits 7–3 Reserved = 2x +1) Bits 10–8 ILVy [2:0] = 2x) Bits 2–0 ILVy [2:0] These bits set the interrupt level of each interrupt. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 70 16-bit timer Ch.2 interrupt (ILVT16_2) ITCLV8 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV17[2:0] IR remote controller interrupt Setup Register 8) (ILVREMC2_0) 7–3 – 0x00 – – 2–0 ILV16[2:0] Sound generator interrupt (ILVSNDA_0) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 71 R/F converter Ch.1 interrupt (ILVRFC_1) ITCLV11 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV23[2:0] P4–P5 port interrupt (ILVPPORT_1) Setup Register 11) 7–3 – 0x00 – 2–0 ILV22[2:0] 12-bit A/D converter interrupt (ILVADC12_0) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 72: O Ports (Pport)

    Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17W34/W35/W36 Item S1C17W34...

  • Page 73: I/O Cell Structure And Functions

    Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 74: Cmos Output And High Impedance State

    • Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 75 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 6.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 76: Port Input/Output Control

    1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”). 2. Configure the input pin combination for key-entry reset using the PCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 77: Interrupts

    These bits are used to set data to be output from the GPIO port pins. 1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 78: Px Port Enable Register

    PxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 79: Px Port Interrupt Flag Register

    PxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 80: Px Port Function Select Register

    Table 6.6.2 Key-Entry Reset Function Settings PCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 81: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 6-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 82: Control Register And Port Function Configuration Of This Ic

    RFC Ch.1 REF1 UPMUX – – – – RFC Ch.1 SENA1 UPMUX – – – – RFC Ch.1 SENB1 UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 6-11 (Rev. 1.2)

  • Page 83: P1 Port Group

    – T16B Ch.0 EXCL00 UPMUX ADC12A ADIN04 – – T16B Ch.1 EXCL10 UPMUX ADC12A ADIN05 – – EXOSC UPMUX ADC12A ADIN06 – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 6-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 84: P2 Port Group

    RFC Ch.0 RFCLKO0 UPMUX – – – – RFC Ch.1 RFCLKO1 UPMUX – – – – RTCA2 RTC1S UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 6-13 (Rev. 1.2)

  • Page 85: P3 Port Group

    – – – – UPMUX – – – – – – UPMUX – – – – – – UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 6-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 86: P4 Port Group

    – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 6-15 (Rev. 1.2)

  • Page 87: P5 Port Group

    – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Seiko Epson Corporation 6-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 88: Pd Port Group

    – – – DSIO – – – – – – DCLK – – – – – – – – – – OSC3 – – – – – – OSC4 – – Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 6-17 (Rev. 1.2)

  • Page 89: Common Registers Between Port Groups

    Register) 7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PINTFGRP 15–8 – 0x00 – – (P Port Interrupt Flag 7–6 – – Group Register) P5INT P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation 6-18 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 90: Universal Port Multiplexer (Upmux)

    4. Initialize the peripheral circuit. 5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 91: Control Registers

    Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 92: Watchdog Timer (Wdt2)

    CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDTCLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 93: Operations

    1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDTCTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 94: Operations In Halt And Sleep Modes

    IOSC OSC1 OSC3 EXOSC 1/16,384 1/128 1/16,384 1/8,192 1/8,192 1/4,096 1/4,096 1/2,048 1/2,048 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 95: Wdt2 Control Register

    Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT2 should also be reset concurrently when running WDT2. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 96: Wdt2 Counter Compare Match Register

    These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 97: Real-Time Clock (Rtca2)

    * Indicates the status when the pin is configured for RTCA2. If the port is shared with the RTCA2 output function and other functions, the RTCA2 function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 98: Clock Settings

    · · · · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 99: Operations

    +1 second (for more information on the +1 second correction, refer to “Real-Time Clock Counter Opera- tions”). Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 100: Real-Time Clock Counter Operations

    +1 second (performs +1 second correction) after the counting has resumed by writ- ing 0 to the RTCCTL.RTCHLD bit. Note: If two or more second count-up timings occurred while the RTCCTL.RTCHLD bit = 1, the coun- ter is always corrected for +1 second only. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 101: Stopwatch Control

    Stopwatch 10 Hz RTCINTF.SW10IF 1/10-second counter count up Writing 1 Stopwatch 100 Hz RTCINTF.SW100IF 1/100-second counter count up Writing 1 Theoretical regulation RTCINTF.RTCTRMIF At the end of theoretical regulation operation Writing 1 completion Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 102: Control Registers

    This bit goes 1 when a value is written to the RTCCTL.RTCTRM[6:0] bits. The theoretical regulation takes up to 1 second for execution. This bit reverts to 0 automatically after the theoretical regulation has finished execution. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 103 “Real-Time Clock Counter Operations.” Notes: • Be sure to avoid writing to this bit when the RTCCTL.RTCBSY bit = 1. • Do not write 1 to this bit again while the RTCCTL.RTCADJ bit = 1. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 104: Rtc Second Alarm Register

    Bits 7–0 Reserved RTC Hour/Minute Alarm Register Register name Bit name Initial Reset Remarks RTCALM2 – – – RTCAPA 13–12 RTCHHA[1:0] 11–8 RTCHLA[3:0] – – 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] Bit 15 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 105: Rtc Stopwatch Control Register

    Note: The stopwatch counter stops in sync with the stopwatch clock after 0 is written to the RTCSWCTL.SWRUN bit. Therefore, the counter value may be incremented (+1) from the value at writing 0. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 106: Rtc Main Time Zone Second/1Hz Register

    Note: The counter value may not be read correctly while the 1 Hz counter is running. These bits must be read twice and assume the counter value was read successfully if the two read results are the same. Seiko Epson Corporation 9-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 107: Rtc Main Time Zone Hour/Minute Register

    RTC Time Zone 3 Month/Day Register Register name Bit name Initial Reset Remarks RTCMON1 15–13 – – – RTCMON2 RTCMOH RTCMON3 11–8 RTCMOL[3:0] 7–6 – – 5–4 RTCDH[1:0] 3–0 RTCDL[3:0] Bits 15–13 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 9-11 (Rev. 1.2)

  • Page 108: Rtc Main Time Zone Year/Week Register

    10-year digit and the 1-year digit of the year counter, respectively. The setting/read values are a BCD code within the range from 0 to 99. Note: Be sure to avoid writing to the RTCYARn.RTCYH[3:0]/RTCYL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation 9-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 109: Rtc Interrupt Flag Register

    RTCINTF.1DAYIF bit: 1-day interrupt RTCINTF.1HURIF bit: 1-hour interrupt RTCINTF.1MINIF bit: 1-minute interrupt RTCINTF.1SECIF bit: 1-second interrupt RTCINTF.1_2SECIF bit: 1/2-second interrupt RTCINTF.1_4SECIF bit: 1/4-second interrupt RTCINTF.1_8SECIF bit: 1/8-second interrupt RTCINTF.1_32SECIF bit: 1/32-second interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 9-13 (Rev. 1.2)

  • Page 110: Rtc Interrupt Enable Register

    RTCINTE.1DAYIE bit: 1-day interrupt RTCINTE.1HURIE bit: 1-hour interrupt RTCINTE.1MINIE bit: 1-minute interrupt RTCINTE.1SECIE bit: 1-second interrupt RTCINTE.1_2SECIE bit: 1/2-second interrupt RTCINTE.1_4SECIE bit: 1/4-second interrupt RTCINTE.1_8SECIE bit: 1/8-second interrupt RTCINTE.1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 9-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 111: Supply Voltage Detector (Svd)

    Clock generator CLKDIV[2:0] DBRUN SVDC[4:0] EXSVD Voltage VDSEL comparator SVDDT circuit Detection SVDSC[1:0] SVDIF result counter SVDIE SVDRE[3:0] Interrupt/reset To system reset circuit control circuit To interrupt controller Figure 10.1.1 SVD Configuration Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 10-1 (Rev. 1.2)

  • Page 112: Input Pin And External Connection

    SLEEP mode and SVD stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD is supplied and the SVD operation resumes. Seiko Epson Corporation 10-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 113: Clock Supply In Debug Mode

    SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Char- acteristics” chapter). Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 10-3 (Rev. 1.2)

  • Page 114: Svd Operations

    SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 115: Svd Reset

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 10-5 (Rev. 1.2)

  • Page 116: Svd Control Register

    SVD detection voltage V 0x1e High 0x1d ↑ 0x1c 0x02 ↓ 0x01 0x00, 0x1f Use prohibited For more information, refer to “Supply Voltage Detector Characteristics, SVD detection voltage ” in the “Electrical Characteristics” chapter. Seiko Epson Corporation 10-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 117: Svd Status And Interrupt Flag Register

    This bit indicates the low power supply voltage detection interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 10-7 (Rev. 1.2)

  • Page 118: Svd Interrupt Enable Register

    • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 119: 16-Bit Timers (T16)

    • A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 120: Clock Settings

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 121: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 11-3 (Rev. 1.2)

  • Page 122: Counter Value Read

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 11-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 123: T16 Ch.n Mode Register

    PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 11-5 (Rev. 1.2)

  • Page 124: T16 Ch.n Reload Data Register

    This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 125: T16 Ch.n Interrupt Enable Register

    This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 11-7 (Rev. 1.2)

  • Page 126: Uart (Uart2)

    • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. Figure 12.1.1 shows the UART2 configuration. Table 12.1.1 UART2 Channel Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 127: Input/Output Pins And External Connections

    - UAnCLK.CLKSRC[1:0] bits (Clock source selection) - UAnCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART2 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 12-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 128: Clock Supply In Sleep Mode

    (UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 12-3 (Rev. 1.2)

  • Page 129: Operations

    - Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts) * The initial value of the UAnINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the UA- nINTE.TBEIE bit is set to 1. Seiko Epson Corporation 12-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 130: Data Transmission

    Read the UAnINTF.TBEIF bit UAnINTF.TBEIF = 1 ? Write transmit data to the UAnTXD register Transmit data remained? Wait for an interrupt request (UAnINTF.TBEIF = 1) Figure 12.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 12-5 (Rev. 1.2)

  • Page 131: Data Reception

    Read receive data (1 byte) from the UAnRXD register the UAnRXD register Read receive data (1 byte) from the UAnRXD register Receive data remained? Receive data remained? Figure 12.5.3.2 Data Reception Flowcharts Seiko Epson Corporation 12-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 132: Irda Interface

    The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.FEIF bit (framing error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 12-7 (Rev. 1.2)

  • Page 133: Parity Error

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 12-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 134: Control Registers

    UART2 Ch.n Mode Register Register name Bit name Initial Reset Remarks UAnMOD 15–11 – 0x00 – – BRDIV INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Bits 15–11 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 12-9 (Rev. 1.2)

  • Page 135: Uart2 Ch.n Baud-Rate Register

    Note: The UAnMOD register settings can be altered only when the UAnCTL.MODEN bit = 0. UART2 Ch.n Baud–Rate Register Register name Bit name Initial Reset Remarks UAnBR 15–12 – – – 11–8 FMD[3:0] 7–0 BRT[7:0] 0x00 Seiko Epson Corporation 12-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 136: Uart2 Ch.n Control Register

    Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte FIFO, and older received data is read first. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 12-11 (Rev. 1.2)

  • Page 137: Uart2 Ch.n Status And Interrupt Flag Register

    UAnINTF.PEIF bit: Parity error interrupt UAnINTF.OEIF bit: Overrun error interrupt UAnINTF.RB2FIF bit: Receive buffer two bytes full interrupt UAnINTF.RB1FIF bit: Receive buffer one byte full interrupt UAnINTF.TBEIF bit: Transmit buffer empty interrupt Seiko Epson Corporation 12-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 138: Uart2 Ch.n Interrupt Enable Register

    UAnINTE.PEIE bit: Parity error interrupt UAnINTE.OEIE bit: Overrun error interrupt UAnINTE.RB2FIE bit: Receive buffer two bytes full interrupt UAnINTE.RB1FIE bit: Receive buffer one byte full interrupt UAnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 12-13 (Rev. 1.2)

  • Page 139: Synchronous Serial Interface (Spia)

    • Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17W34/W35/W36 Item S1C17W34...

  • Page 140: Input/Output Pins And External Connections

    SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 13.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 13-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 141: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 13-3 (Rev. 1.2)

  • Page 142: Clock Supply In Debug Mode

    SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 13.3.3.1 SPI Clock Phase and Polarity (SPInMOD.LSBFST bit = 0, SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 143: Data Format

    1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 13-5 (Rev. 1.2)
  • Page 144 SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 145: Data Reception In Master Mode

    Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 13.5.3.1 Example of Data Receiving Operations in Master Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 13-7 (Rev. 1.2)

  • Page 146: Terminating Data Transfer In Master Mode

    SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 147 Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 13-9 (Rev. 1.2)

  • Page 148: Terminating Data Transfer In Slave Mode

    “Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 149: Control Registers

    Remarks SPInMOD 15–12 – – – 11–8 CHLN[3:0] 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL Bits 15–12 Reserved Bits 11–8 CHLN[3:0] These bits set the bit length of transfer data. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 13-11 (Rev. 1.2)

  • Page 150: Spia Ch.n Control Register

    Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 151: Spia Ch.n Transmit Data Register

    0x00 – – 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 13-13 (Rev. 1.2)

  • Page 152: Spia Ch.n Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 153: C (I2C)

    • Master mode supports automatic bus clear sending function. • Can generate receive buffer full, transmit buffer empty, and other interrupts. Figure 14.1.1 shows the I2C configuration. Table 14.1.1 I2C Channel Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 154: Input/Output Pins And External Connections

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 155: Clock Settings

    14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-3 (Rev. 1.2)

  • Page 156: Operations

    - Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 157: Data Transmission In Master Mode

    I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-5 (Rev. 1.2)
  • Page 158 Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 159: Data Reception In Master Mode

    This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-7 (Rev. 1.2)
  • Page 160 Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 161: 10-Bit Addressing In Master Mode

    Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-9 (Rev. 1.2)

  • Page 162: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 163 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-11 (Rev. 1.2)

  • Page 164: Data Reception In Slave Mode

    I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 165 Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-13 (Rev. 1.2)

  • Page 166: Slave Operations In 10-Bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 167: Error Detection

    4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-15 (Rev. 1.2)

  • Page 168: Interrupts

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2CnOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation 14-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 169: Control Registers

    (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-17 (Rev. 1.2)

  • Page 170: I2C Ch.n Mode Register

    The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 171: I2C Ch.n Control Register

    Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-19 (Rev. 1.2)

  • Page 172: I2C Ch.n Transmit Data Register

    0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 173: I2C Ch.n Interrupt Enable Register

    Transmit buffer empty interrupt I2C Ch.n Interrupt Enable Register Register name Bit name Initial Reset Remarks I2CnINTE 15–8 – 0x00 – – BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Bits 15–8 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 14-21 (Rev. 1.2)
  • Page 174 I2CnINTE.NACKIE bit: NACK reception interrupt I2CnINTE.STOPIE bit: STOP condition interrupt I2CnINTE.STARTIE bit: START condition interrupt I2CnINTE.ERRIE bit: Error detection interrupt I2CnINTE.RBFIE bit: Receive buffer full interrupt I2CnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 14-22 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 175: 16-Bit Pwm Timers (T16B)

    - The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35 S1C17W36 Number of channels 3 channels (Ch.0 to Ch.2)

  • Page 176: Input/Output Pins

    If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 177: Clock Settings

    Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-3 (Rev. 1.2)

  • Page 178: Operations

    - T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 179: Counter Block Operations

    MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-5 (Rev. 1.2)
  • Page 180 MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 181 Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-7 (Rev. 1.2)

  • Page 182: Comparator/Capture Block Operations

    MAX value (T16BnMC register) Counter Comparison value (T16BnCCRm register) Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 183 (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-9 (Rev. 1.2)
  • Page 184 (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 185 (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-11 (Rev. 1.2)
  • Page 186 (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 187 Compare period during counting down Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-13 (Rev. 1.2)
  • Page 188 If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 189 Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16BnCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16BnTC.TC[15:0] Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation Figure 15.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-15 (Rev. 1.2)

  • Page 190: Tout Output Control

    The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 191 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-17 (Rev. 1.2)
  • Page 192 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.2 TOUT Output Waveform (T16BnCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation 15-18 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 193 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-19 (Rev. 1.2)
  • Page 194 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 15-20 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 195 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.3 TOUT Output Waveform (T16BnCCCTL0.TOUTMT bit = 1, T16BnCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-21 (Rev. 1.2)

  • Page 196: Interrupt

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 197: T16B Ch.n Counter Control Register

    T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-23 (Rev. 1.2)

  • Page 198: T16B Ch.n Max Counter Data Register

    T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 199: T16B Ch.n Counter Status Register

    This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-25 (Rev. 1.2)

  • Page 200: T16B Ch.n Interrupt Flag Register

    Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 201: T16B Ch.n Interrupt Enable Register

    The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-27 (Rev. 1.2)

  • Page 202: T16B Ch.n Comparator/Capture M Control Register

    These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 203 The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 15-29 (Rev. 1.2)

  • Page 204: T16B Ch.n Compare/Capture M Data Register

    In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 205: Sound Generator (Snda)

    Clock generator DBRUN MODEN SBSY Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt controller Interrupt control circuit EMIE EMIF EDIE EDIF Figure 16.1.1 SNDA Configuration Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-1 (Rev. 1.2)

  • Page 206: Output Pins And External Connections

    Piezoelectric buzzer #BZOUT S1C17 SNDA Figure 16.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C17 SNDA Figure 16.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 16-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 207: Clock Settings

    IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-3 (Rev. 1.2)
  • Page 208 Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 209 – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-5 (Rev. 1.2)

  • Page 210: Buzzer Output In One-Shot Buzzer Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 211: Output In Melody Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-7 (Rev. 1.2)
  • Page 212 = 32,768 Hz) CLK_SNDA SNDDAT.SFRQ[7:0] bits Scale Frequency [Hz] 0xf8 131.60 0xea 139.44 0xdd 147.60 0xd1 156.04 0xc5 165.49 0xba 175.23 0xaf 186.18 0xa5 197.40 0x9c 208.71 0x93 221.41 0x8b 234.06 Seiko Epson Corporation 16-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 213: Interrupts

    This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-9 (Rev. 1.2)

  • Page 214: Snda Select Register

    187.5 43.6 171.9 156.3 53.3 140.6 125.0 68.6 109.4 93.8 78.1 62.5 46.9 31.3 15.6 Note: Be sure to avoid altering these bits when SNDINTF.SBSY bit = 1. Bits 7–3 Reserved Seiko Epson Corporation 16-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 215: Snda Control Register

    This bit specifies a tie or slur (continuous play with the previous note) in melody mode. 1 (R/W): Enable tie/slur 0 (R/W): Disable tie/slur This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-11 (Rev. 1.2)

  • Page 216: Snda Interrupt Flag Register

    No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 217: Snda Interrupt Enable Register

    These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: SNDINTE.EMIE bit: Sound buffer empty interrupt SNDINTE.EDIE bit: Sound output completion interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 16-13 (Rev. 1.2)

  • Page 218: Ir Remote Controller (Remc2)

    • Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 17.1.1 shows the REMC2 configuration. Table 17.1.1 REMC2 Channel Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 219: External Connections

    1. Write 1 to the REMDBCTL.REMCRST bit. (Reset REMC2) 2. Configure the REMCLK.CLKSRC[1:0] and REMCLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC2 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 17-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 220: Data Transmission Procedures

    The REMC2 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 17.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 17-3 (Rev. 1.2)
  • Page 221 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REM- DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC2 and the setting values of the REMAPLEN. APLEN[15:0] and REMDBLEN.DBLEN[15:0] bits. Figure 17.4.3.3 shows an example of the data signal gen- erated. Seiko Epson Corporation 17-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 222: Continuous Data Transmission And Compare Buffers

    (REMDBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMDBLEN.DBLEN[15:0] bit-setting value. 17.4.4 Continuous Data Transmission and Compare Buffers Figure 17.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 17-5 (Rev. 1.2)

  • Page 223: Interrupts

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 17-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 224: Application Example: Driving El Lamp

    1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC2 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 17-7 (Rev. 1.2)

  • Page 225: Remc2 Data Bit Counter Control Register

    This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 17-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 226: Remc2 Data Bit Counter Register

    0x0000 H0/S0 Cleared by writing 1 to the REMDBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 17-9 (Rev. 1.2)

  • Page 227: Remc2 Data Bit Active Pulse Length Register

    This bit indicates whether the value written to the REMAPLEN.APLEN[15:0] bits is transferred to the REMAPLEN buffer or not. (See Figure 17.4.4.1.) 1 (R): Transfer to the REMAPLEN buffer has not completed. 0 (R): Transfer to the REMAPLEN buffer has completed. Seiko Epson Corporation 17-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 228: Remc2 Interrupt Enable Register

    These bits set the carrier signal cycle. A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 17-11 (Rev. 1.2)

  • Page 229: Remc2 Carrier Modulation Control Register

    This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 17-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 230: Lcd Driver (Lcd32B)

    • The LCD contrast is adjustable into 16 steps. • Includes a power supply for 1/4 bias and 1/5 bias driving (allows external voltages to be applied). • Can generate interrupts every frame. Figure 18.1.1 shows the LCD32B configuration. Table 18.1.1 LCD32B Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 231: Output Pins And External Connections

    2. Set the following LCD32CLK register bits: - LCD32CLK.CLKSRC[1:0] bits (Clock source selection) - LCD32CLK.CLKDIV[2:0] bits (Clock division ratio selection = Clock frequency setting) The CLK_LCD32B frequency should be set to around 32 kHz. Seiko Epson Corporation 18-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 232: Clock Supply In Sleep Mode

    102.4 136.5 204.8 409.6 0x08 56.9 65.0 75.9 91.0 113.8 151.7 227.6 455.1 0x07 64.0 73.1 85.3 102.4 128.0 170.7 256.0 512.0 0x06 73.1 83.6 97.5 117.0 146.3 195.0 292.6 585.1 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-3 (Rev. 1.2)
  • Page 233 1/20 duty 1/19 duty 1/18 duty 1/17 duty 0x1f 0x1e 0x1d 0x1c 0x1b 0x1a 0x19 0x18 0x17 10.0 0x16 10.5 0x15 10.3 11.0 0x14 10.3 10.8 11.5 0x13 10.2 10.8 11.4 12.0 Seiko Epson Corporation 18-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 234 36.6 37.9 39.4 41.0 0x02 42.7 44.0 45.5 47.1 48.8 50.6 52.5 54.6 0x01 64.0 66.1 68.3 70.6 73.1 75.9 78.8 81.9 0x00 128.0 132.1 136.5 141.2 146.3 151.7 157.5 163.8 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-5 (Rev. 1.2)

  • Page 235: Lcd Power Supply

    LCD1 When 1/4 bias is selected (LCD8PWR.BIASSEL bit = 1) When 1/5 bias is selected (LCD8PWR.BIASSEL bit = 0) Figure 18.4.2.1 External Connection Example for External Voltage Application Mode (Resistor Divider) Seiko Epson Corporation 18-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 236: Lcd Voltage Regulator Settings

    8. Write display data to the display data RAM. 9. Set the following bits when using the interrupt: - Write 1 to the LCD32INTF.FRMIF bit. (Clear interrupt flag) - Set the LCD32INTE.FRMIE bit to 1. (Enable LCD32B interrupt) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-7 (Rev. 1.2)

  • Page 237: Display On/Off

    1/24 COM0–COM23 1,536 0x16 1/23 COM0–COM22 1,472 0x15 1/22 COM0–COM21 1,408 0x14 1/21 COM0–COM20 1,344 0x13 1/20 COM0–COM19 1,280 0x12 1/19 COM0–COM18 1,216 0x11 1/18 COM0–COM17 1,152 0x10 1/17 COM0–COM16 1,088 Seiko Epson Corporation 18-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 238 SEG77 SEG77 COM18 SEG78/COM17 SEG78 SEG78 COM17 SEG79/COM16 SEG79 SEG79 COM16 *1 The COM pins to be used depend on the drive duty selection. For more information, refer to Table 18.5.4.1. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-9 (Rev. 1.2)

  • Page 239: Drive Waveforms

    COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM24 COM25 COM26 COM28 COM2 COM29 COM30 COM31 SEGx COM30 COM31 SEGx Figure 18.5.5.1 1/32 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation 18-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 240 COM29 COM30 COM31 (= V SEGx COM30 (= V COM31 (= V (= V (= V SEGx (= V (= V (= V Figure 18.5.5.2 1/32 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-11 (Rev. 1.2)
  • Page 241 COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM2 COM13 COM14 COM15 SEGx COM14 COM15 SEGx Figure 18.5.5.3 1/16 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation 18-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 242 COM13 COM14 COM15 (= V SEGx COM14 (= V COM15 (= V (= V (= V SEGx (= V (= V (= V Figure 18.5.5.4 1/16 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-13 (Rev. 1.2)
  • Page 243 18 LCD DRIVER (LCD32B) 1 frame LFRO display status COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM7 SEGx COM2 COM6 COM7 SEGx Figure 18.5.5.5 1/8 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation 18-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 244 SEGx (= V COM2 (= V COM6 (= V COM7 (= V (= V (= V SEGx (= V (= V (= V Figure 18.5.5.6 1/8 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-15 (Rev. 1.2)

  • Page 245: Partial Common Output Drive

    Note that using the n-line inverse AC drive function increases current consumption. Table 18.5.7.1 Selecting Number of Inverse Lines LCD32TIM2.NLINE[4:0] bits Number of inverse lines 0x1f 31 lines 0x1e 30 lines 0x01 1 line 0x00 Normal drive Seiko Epson Corporation 18-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 246: Display Data Ram

    When the LCD32DSP.COMREV bit is set to 1, memory bits are assigned to common pins in ascending order. When the LCD32DSP.COMREV bit is set to 0, memory bits are assigned to common pins in descending order. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-17 (Rev. 1.2)
  • Page 247 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0 LCD32DSP.SEGREV · · · bit = 1 LCD32DSP.SEGREV · · · bit = 0 (a) LCD32TIM1.COMLOC bit = 0 Seiko Epson Corporation 18-18 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 248 COM30 COM1 COM31 COM0 LCD32DSP.SEGREV · · · bit = 1 LCD32DSP.SEGREV · · · bit = 0 (b) LCD32TIM1.COMLOC bit = 1 Figure 18.6.3.1 Display Data RAM Map (1/32 duty) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-19 (Rev. 1.2)
  • Page 249 COM20 COM3 COM21 COM2 COM22 COM1 COM23 COM0 Unused area (general-purpose RAM) LCD32DSP.SEGREV · · · bit = 1 LCD32DSP.SEGREV · · · bit = 0 (a) LCD32TIM1.COMLOC bit = 0 Seiko Epson Corporation 18-20 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 250 Unused area (general-purpose RAM) LCD32DSP.SEGREV · · · bit = 1 LCD32DSP.SEGREV · · · bit = 0 (b) LCD32TIM1.COMLOC bit = 1 Figure 18.6.3.2 Display Data RAM Map (1/24 duty) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-21 (Rev. 1.2)
  • Page 251 COM2 COM14 COM1 COM15 COM0 Unused area (general-purpose RAM) LCD32DSP.SEGREV · · · bit = 1 LCD32DSP.SEGREV · · · bit = 0 Figure 18.6.3.3 Display Data RAM Map (1/16 duty) Seiko Epson Corporation 18-22 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 252 Display area 1 COM0 COM0 Unused area (general-purpose RAM) LCD32DSP.SEGREV · · · bit = 1 LCD32DSP.SEGREV · · · bit = 0 Figure 18.6.3.4 Display Data RAM Map (static drive) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-23 (Rev. 1.2)

  • Page 253: Interrupt

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD32B operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD32B. Seiko Epson Corporation 18-24 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 254: Lcd32B Control Register

    12–8 FRMCNT[4:0] 0x01 7–6 – – COMLOC 4–0 LDUTY[4:0] 0x1f Bits 15–13 Reserved Bits 12–8 FRMCNT[4:0] These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–6 Reserved Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-25 (Rev. 1.2)

  • Page 255: Lcd32B Timing Control Register 2

    LCD32PWR.EXVCSEL bit to V is set to 0, as the LCD power supply pins are short-circuited to GND. Bits 14–12 Reserved Bits 11–8 LC[3:0] These bits set the LCD panel contrast. Seiko Epson Corporation 18-26 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 256 1–0 DSPC[1:0] Bits 15–7 Reserved Bit 6 SEGREV This bit selects the segment pin assignment direction. 1 (R/W): Normal assignment 0 (R/W): Inverse assignment For more information, see Figures 18.6.3.1 to 18.6.3.4. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-27 (Rev. 1.2)

  • Page 257: Lcd32B Com Pin Control Registers 0 And 1

    COM12DEN COM11DEN COM10DEN COM9DEN COM8DEN COM7DEN COM6DEN COM5DEN COM4DEN COM3DEN COM2DEN COM1DEN COM0DEN LCD32COMC1 COM31DEN – COM30DEN COM29DEN COM28DEN COM27DEN COM26DEN COM25DEN COM24DEN COM23DEN COM22DEN COM21DEN COM20DEN COM19DEN COM18DEN COM17DEN COM16DEN Seiko Epson Corporation 18-28 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 258: Lcd32B Interrupt Flag Register

    LCD32INTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 18-29 (Rev. 1.2)

  • Page 259: F Converter (Rfc)

    • Provides an output and continuous oscillation function for monitoring the oscillation frequency. • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 19.1.1 shows the RFC configuration. Table 19.1.1 RFC Channel Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 260: Input/Output Pins And External Connections

    Figure 19.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Reference capacitor Figure 19.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 19-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 261: Clock Settings

    (Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 19-3 (Rev. 1.2)

  • Page 262: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 19-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 263: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 19-5 (Rev. 1.2)

  • Page 264: Forced Termination

    Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 19.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 19-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 265: Cr Oscillation Frequency Monitoring Function

    For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 19-7 (Rev. 1.2)

  • Page 266: Control Registers

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 19-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 267: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 19-9 (Rev. 1.2)

  • Page 268: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 19-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 269: Rfc Ch.n Interrupt Flag Register

    RFCnINTE.OVTCIE bit: Time base counter overflow error interrupt RFCnINTE.OVMCIE bit: Measurement counter overflow error interrupt RFCnINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFCnINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFCnINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 19-11 (Rev. 1.2)

  • Page 270: 12-Bit A/D Converter (Adc12A)

    2. 16-bit timer underflow trigger 3. External trigger • Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. Figure 20.1.1 shows the ADC12A configuration. Table 20.1.1 ADC12A Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35 S1C17W36 Number of channels 1 channel (Ch.0)

  • Page 271: Input Pins And External Connections

    : acquisition time). Figure 20.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 20.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 20-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 272: Operations

    A/D conversion is actually started in sync with CLK_T16_k after a trigger is accepted. Writing 0 to the ADC12_nCTL.ADST bit stops A/D conversion after the one currently being executed has com- pleted. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 20-3 (Rev. 1.2)

  • Page 273: Conversion Mode And Analog Input Pin Settings

    3. Read the A/D conversion result of the analog input m (ADC12_nADmD.ADmD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 20-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 274 ADINn4 ADINn4 ADC12_nAD3D.AD3D[15:0] ADINn3 conversion result (first) ADINn3 conversion result (second) ADC12_nAD4D.AD4D[15:0] ADINn4 conversion result (first) ADINn4 conversion result (second) Cleared Cleared ADC12_nINTF.AD3CIF Cleared Cleared ADC12_nINTF.AD4CIF Figure 20.4.4.1 A/D Conversion Operations Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 20-5 (Rev. 1.2)

  • Page 275: Interrupts

    (ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. Bit 11 Reserved Seiko Epson Corporation 20-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 276: Adc12A Ch.n Trigger/Analog Input Select Register

    ENDAIN[2:0] bits ≥ ADC12_nTRG.STAAIN[2:0] bits. Bits 10–8 STAAIN[2:0] These bits set the analog input pin to be A/D converted first. See Table 20.6.1 for the relationship between analog input pins and bit setting values. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 20-7 (Rev. 1.2)

  • Page 277: Adc12A Ch.n Configuration Register

    Note: Make sure that the ADC12_nCTL.BSYSTAT bit is set to 0 before altering the ADC12_nCFG register. Bits 15–2 Reserved Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. Seiko Epson Corporation 20-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 278: Adc12A Ch.n Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: ADC12_nINTF.ADmOVIF bit: Analog input signal m A/D conversion result overwrite error interrupt ADC12_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 20-9 (Rev. 1.2)

  • Page 279: Adc12A Ch.n Interrupt Enable Register

    ADC12A Ch.n Result Register m Register name Bit name Initial Reset Remarks ADC12_nADmD 15–0 ADmD[15:0] 0x0000 – Bits 15–0 ADmD[15:0] These bits are the A/D conversion results of the analog input signal m. Seiko Epson Corporation 20-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 280: Temperature Sensor/Reference Voltage Generator (Tsrvr)

    A/D converter. • Can supply the reference voltage generated in this circuit to external devices if this IC has the VREFA exclusive pin. Figure 21.1.1 shows the TSRVR configuration. Table 21.1.1 TSRVR Configuration of S1C17W34/W35/W36 Item S1C17W34 S1C17W35...

  • Page 281: External Connections

    ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 21-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 282: Control Registers

    TSRVRnVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVRnVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external volt- age to the VREFAm pin. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 21-3 (Rev. 1.2)

  • Page 283: Multiplier/Divider (Copro2)

    %rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 22.2.1 Mode Setting Register Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 22-1 (Rev. 1.2)

  • Page 284: Multiplication

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output (16 bits) Flag output Figure 22.3.1 Data Path in Multiplication Mode Seiko Epson Corporation 22-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 285: Division

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 22.4.1 Data Path in Initialize Mode 2 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 22-3 (Rev. 1.2)
  • Page 286 %rd ← res1[31:16] (Remainder) (ext imm9) res0[31:0] ÷ {%rd, imm7/16} ld.ca %rd,imm7 res0[31:0] ← Quotient res1[31:0] ← Remainder %rd ← res1[31:16] (Remainder) res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation 22-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 287: Mac

    COPRO2 Argument 2 16 bits Argument 1 32 bits S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 22.5.1 Data Path in Initialize Mode Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 22-5 (Rev. 1.2)
  • Page 288 %r0. ld.cw %r0,0x13 ; Sets the mode (operation result read mode and 16 high-order bits output mode 0). ; Loads the 16 high-order bits of the result to %r1. ld.ca %r1,%r0 Seiko Epson Corporation 22-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 289: Reading Operation Results

    %rd,%rs 0x23 %rd ← res1[15:0] ld.ca %rd,imm7 %rd ← res1[15:0] ld.ca %rd,%rs 0x33 %rd ← res1[31:16] ld.ca %rd,imm7 %rd ← res1[31:16] res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 22-7 (Rev. 1.2)

  • Page 290: Electrical Characteristics

    Oscillation resistor for OSC3 oscillator When the CR oscillator is used – 1,000 DSIO pull-up resistor – – Capacitor between V and V – – µF Capacitor between V and VREFA – – µF VREFA Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-1 (Rev. 1.2)

  • Page 291: Current Consumption

    , SYSCLK = OSC3 *1 OSC1 oscillator: CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1.OSDEN bit = 0, = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) *2 OSC3 oscillator: CLGOSC3.OSC3MD[1:0] bits = 0x2, CLGOSC3.OSC3INV[1:0] bits = 0x0, C...
  • Page 292 Ta [°C] Current consumption-frequency characteristic in RUN mode (OSC3 operation) IIOSC = OFF, OSC1 = 32 kHz, OSC3 = ON, Ta = 25 °C, Typ. value Internal oscillator Ceramic oscillator [MHz] OSC3 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-3 (Rev. 1.2)

  • Page 293: System Reset Controller (Src) Characteristics

    Oscillation start time – – µs Oscillation frequency 25 °C 1.6 to 3.6 V IOSC 1.2 to 1.6 V 1.6 to 3.6 V -40 to 85 °C 1.2 to 1.6 V Seiko Epson Corporation 23-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 294 CLGOSC1.OSDEN bit = 1 – 0.025 µA OSD1 *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC3 oscillator circuit characteristics Unless otherwise specified: V = 1.2 to 3.6 V, V = 0 V, Ta = 25 °C...
  • Page 295 0.8 × V Low level Schmitt input threshold voltage 0.2 × V – 0.5 × V Schmitt input hysteresis voltage – – = 1/f = 1/f EXOSC EXOSC EXOSC EXOSC EXOSCH EXOSCH EXOSC Seiko Epson Corporation 23-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 296: Flash Memory Characteristics

    Ta = 85 °C, Min. value –V = 1.2 V = 3.6 V = 1.6 V = 1.6 V = 1.2 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 = 3.6 V Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-7 (Rev. 1.2)

  • Page 297: Supply Voltage Detector (Svd) Characteristics

    3.49 SVDCTL.SVDC[4:0] bits = 0x1d 3.41 3.50 3.59 SVDCTL.SVDC[4:0] bits = 0x1e 3.51 3.60 3.69 SVD circuit enable response time – – µs SVDEN SVD circuit response time – – µs Seiko Epson Corporation 23-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 298: Uart (Uart2) Characteristics

    Transfer baud rate Normal mode 1.6 to 3.6 V – 460,800 BRT1 1.2 to 1.6 V – 57,600 IrDA mode 1.6 to 3.6 V – 115,200 BRT2 1.2 to 1.6 V – 57,600 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-9 (Rev. 1.2)

  • Page 299: Synchronous Serial Interface (Spia) Characteristics

    (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation 23-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 300: I 2 C (I2C) Characteristics

    4.12 4.33 4.55 LCD32PWR.LC[3:0] bits = 0xc 4.18 4.40 4.62 LCD32PWR.LC[3:0] bits = 0xd 4.24 4.46 4.68 LCD32PWR.LC[3:0] bits = 0xe 4.29 4.52 4.75 LCD32PWR.LC[3:0] bits = 0xf 4.35 4.58 4.81 Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-11 (Rev. 1.2)
  • Page 301 *1 Other LCD driver settings: LCD32PWR.LC[3:0] bits = 0xf, CLK_LCD32B = 32 kHz, LCD32TIM1.FRMCNT[4:0] bits = 0x01 (frame frequency = 64 Hz) *2 The value is added to the current consumption in HALT/RUN mode. Current consumption increases according to the display contents and panel load. Seiko Epson Corporation 23-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 302 Ta = 25 °C, Typ. value, LCD32PWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only when a load is connected to the V pin only [µA] [µA] Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-13 (Rev. 1.2)

  • Page 303: R/F Converter (Rfc) Characteristics

    = 100 kW, Ta = 25 °C, Typ. value 10,000 1,000 1,000 3.6 V 1.6 V 1.2 V 3.6 V 1.6 V ∆f /∆IC 1.2 V RFCLK ∆f /∆IC RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation 23-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 304: 12-Bit A/D Converter (Adc12A) Characteristics

    A/D converter current consumption-power supply voltage characteristic , ADIN = V /2, f = 50 ksps, Ta = 25 °C, Typ. value REFA REFA 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 REFA Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 23-15 (Rev. 1.2)

  • Page 305: Temperature Sensor/Reference Voltage Generator (Tsrvr) Characteristics

    – – µs TEMP 0x1–0x3 TSRVRnVCTL.VREFAMD[1:0] Invalid Valid VREFAn VREFA TSRVRnTCTL.TEMPEN Invalid Valid Temperature sensor output TEMP Temperature sensor output voltage-temperature characteristic = 2.2 to 3.6 V, Typ. value Ta [°C] Seiko Epson Corporation 23-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 306: Basic External Connection Diagram

    *3: When 1/4 bias is selected *4: When 1/5 bias is selected *5: When OSC3 CR oscillator is selected *6: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 24-1 (Rev. 1.2)
  • Page 307 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...

  • Page 308: Package

    25 PACKAGE 25 Package QFP21-176PIN (P-LQFP176-2424-0.50) (Unit: mm) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.75 Figure 25.1 QFP21-176PIN Package Dimensions Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL 25-1 (Rev. 1.2)

  • Page 309: Appendix A List Of Peripheral Circuit Control Registers

    WUPMD R/WP – (CLG System Clock – – Control Register) 13–12 WUPDIV[1:0] R/WP 11–10 – – 9–8 WUPSRC[1:0] R/WP 7–6 – – 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-1 (Rev. 1.2)
  • Page 310 – Register) (reserved) OSC1STPIE IOSCTEDIE – – OSC3STAIE OSC1STAIE IOSCSTAIE 0x4050 CLGFOUT0 15–8 – 0x00 – – (CLG FOUT Control – – Register 0) 6–4 FOUTDIV[2:0] 3–2 FOUTSRC[1:0] – – FOUTEN Seiko Epson Corporation AP-A-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 311 0x408c ITCLV6 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV13[2:0] UART Ch.1 interrupt Setup Register 6) (ILVUART2_1) 7–3 – 0x00 – – 2–0 ILV12[2:0] 16-bit PWM timer Ch.2 interrupt (ILVT16B_2) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-3 (Rev. 1.2)
  • Page 312 Register) STATNMI 7–5 – – WDTCNTRST Always read as 0. 3–0 WDTRUN[3:0] R/WP – 0x40a4 WDTCMP 15–10 – 0x00 – – (WDT2 Counter Com- 9–0 CMP[9:0] 0x3ff R/WP pare Match Register) Seiko Epson Corporation AP-A-4 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 313: 0X40C0-0X40E6 Real-Time Clock (Rtca2)

    13–12 RTCHH[1:0] 11–8 RTCHL[3:0] – – 6–4 RTCMIH[2:0] 3–0 RTCMIL[3:0] 0x40cc RTCMON1 15–13 – – – (RTC Main Time Zone RTCMOH Month/Day Register) 11–8 RTCMOL[3:0] 7–6 – – 5–4 RTCDH[1:0] 3–0 RTCDL[3:0] Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-5 (Rev. 1.2)
  • Page 314 13–12 RTCHH[1:0] 11–8 RTCHL[3:0] – – 6–4 RTCMIH[2:0] 3–0 RTCMIL[3:0] 0x40dc RTCMON2 15–13 – – – (RTC Time Zone 2 RTCMOH Month/Day Register) 11–8 RTCMOL[3:0] 7–6 – – 5–4 RTCDH[1:0] 3–0 RTCDL[3:0] Seiko Epson Corporation AP-A-6 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 315 (SVD Status and In- SVDDT – terrupt Flag Register) 7–1 – 0x00 – SVDIF Cleared by writing 1. 0x4106 SVDINTE 15–8 – 0x00 – – (SVD Interrupt Enable 7–1 – 0x00 – Register) SVDIE Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-7 (Rev. 1.2)

  • Page 316: Flash Controller (Flashc)

    Flag Register) 0x4208 P0INTCTL 15–8 P0EDGE[7:0] 0x00 – (P0 Port Interrupt 7–0 P0IE[7:0] 0x00 Control Register) 0x420a P0CHATEN 15–8 – 0x00 – – (P0 Port Chattering Filter Enable 7–0 P0CHATEN[7:0] 0x00 Register) Seiko Epson Corporation AP-A-8 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 317 15–8 – 0x00 – – (P2 Port Interrupt 7–0 P2IF[7:0] 0x00 Cleared by writing 1. Flag Register) 0x4228 P2INTCTL 15–8 P2EDGE[7:0] 0x00 – (P2 Port Interrupt 7–0 P2IE[7:0] 0x00 Control Register) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-9 (Rev. 1.2)
  • Page 318 15–8 P4PDPU[7:0] 0x00 – (P4 Port Pull-up/down 7–0 P4REN[7:0] 0x00 Control Register) 0x4246 P4INTF 15–8 – 0x00 – – (P4 Port Interrupt 7–0 P4IF[7:0] 0x00 Cleared by writing 1. Flag Register) Seiko Epson Corporation AP-A-10 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 319 (Pd Port Mode Select 7–5 – – Register) 4–0 PDSEL[4:0] 0x07 0x42de PDFNCSEL 15–10 – 0x00 – – (Pd Port Function 9–8 PD4MUX[1:0] Select Register) 7–6 PD3MUX[1:0] 5–4 PD2MUX[1:0] 3–2 PD1MUX[1:0] 1–0 PD0MUX[1:0] Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-11 (Rev. 1.2)
  • Page 320 10–8 P11PERISEL[2:0] Setting Register) 7–5 P10PPFNC[2:0] 4–3 P10PERICH[1:0] 2–0 P10PERISEL[2:0] 0x430a P1UPMUX1 15–13 P13PPFNC[2:0] – (P12–13 Universal 12–11 P13PERICH[1:0] Port Multiplexer 10–8 P13PERISEL[2:0] Setting Register) 7–5 P12PPFNC[2:0] 4–3 P12PERICH[1:0] 2–0 P12PERISEL[2:0] Seiko Epson Corporation AP-A-12 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 321 10–8 P33PERISEL[2:0] Setting Register) 7–5 P32PPFNC[2:0] 4–3 P32PERICH[1:0] 2–0 P32PERISEL[2:0] 0x431c P3UPMUX2 15–13 P35PPFNC[2:0] – (P34–35 Universal 12–11 P35PERICH[1:0] Port Multiplexer 10–8 P35PERISEL[2:0] Setting Register) 7–5 P34PPFNC[2:0] 4–3 P34PERICH[1:0] 2–0 P34PERISEL[2:0] Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-13 (Rev. 1.2)
  • Page 322 UA0RXD register. PEIF H0/S0 OEIF H0/S0 Cleared by writing 1. RB2FIF H0/S0 Cleared by reading the UA0RXD register. RB1FIF H0/S0 TBEIF H0/S0 Cleared by writing to the UA0TXD register. Seiko Epson Corporation AP-A-14 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 323 LSBFST CPHA CPOL 0x43b2 SPI0CTL 15–8 – 0x00 – – (SPIA Ch.0 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x43b4 SPI0TXD 15–0 TXD[15:0] 0x0000 – (SPIA Ch.0 Transmit Data Register) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-15 (Rev. 1.2)
  • Page 324 MODEN 0x43cc I2C0TXD 15–8 – 0x00 – – (I2C Ch.0 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x43ce I2C0RXD 15–8 – 0x00 – – (I2C Ch.0 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation AP-A-16 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 325 Counter Data Register) 0x5006 T16B0TC 15–0 TC[15:0] 0x0000 – (T16B Ch.0 Timer Counter Data Register) 0x5008 T16B0CS 15–8 – 0x00 – – (T16B Ch.0 Counter 7–4 – – Status Register) CAPI1 CAPI0 UP_DOWN Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-17 (Rev. 1.2)
  • Page 326 16-bit PWM Timer (T16B) Ch.1 Address Register name Bit name Initial Reset Remarks 0x5040 T16B1CLK 15–9 – 0x00 – – (T16B Ch.1 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] – – 2–0 CLKSRC[2:0] Seiko Epson Corporation AP-A-18 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 327 14–12 CBUFMD[2:0] Capture 0 Control 11–10 CAPIS[1:0] Register) 9–8 CAPTRG[1:0] – – TOUTMT TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD 0x5052 T16B1CCR0 15–0 CC[15:0] 0x0000 – (T16B Ch.1 Compare/ Capture 0 Data Register) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-19 (Rev. 1.2)
  • Page 328 – Status Register) CAPI1 CAPI0 UP_DOWN 0x508a T16B2INTF 15–8 – 0x00 – – (T16B Ch.2 Interrupt 7–6 – – Flag Register) CAPOW1IF Cleared by writing 1. CMPCAP1IF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF Seiko Epson Corporation AP-A-20 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 329 – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x5202 UA1MOD 15–11 – 0x00 – – (UART2 Ch.1 Mode BRDIV Register) INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-21 (Rev. 1.2)
  • Page 330 (T16 Ch.2 Control PRUN Register) 7–2 – 0x00 – PRESET MODEN 0x5266 T16_2TR 15–0 TR[15:0] 0xffff – (T16 Ch.2 Reload Data Register) 0x5268 T16_2TC 15–0 TC[15:0] 0xffff – (T16 Ch.2 Counter Data Register) Seiko Epson Corporation AP-A-22 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 331 (SNDA Clock Control DBRUN Register) – – 6–4 CLKDIV[2:0] 3–2 – – 1–0 CLKSRC[1:0] 0x5302 SNDSEL 15–12 – – – (SNDA Select 11–8 STIM[3:0] Register) 7–3 – 0x00 – SINV 1–0 MOSEL[1:0] Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-23 (Rev. 1.2)
  • Page 332 DBLENBSY Effective when the REM- DBCTL.BUFEN bit = 1. APLENBSY 7–2 – 0x00 – – DBIF H0/S0 Cleared by writing 1 to this bit or the REMDBCTL.REM- APIF H0/S0 CRST bit. Seiko Epson Corporation AP-A-24 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 333 11–8 LC[3:0] 7–5 – – BSTEN BIASSEL HVLD – – VCEN 0x540a LCD32DSP 15–8 – 0x00 – – (LCD32B Display – – Control Register) SEGREV COMREV DSPREV – – DSPAR 1–0 DSPC[1:0] Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-25 (Rev. 1.2)
  • Page 334 Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x5442 RFC0CTL 15–9 – 0x00 – – (RFC Ch.0 Control RFCLKMD Register) CONEN EVTEN 5–4 SMODE[1:0] 3–1 – – MODEN Seiko Epson Corporation AP-A-26 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 335 5–4 SMODE[1:0] Setting to 0x1 is invalid. 3–1 – – – MODEN 0x5464 RFC1TRG 15–8 – 0x00 – – (RFC Ch.1 Oscillation 7–3 – 0x00 – Trigger Register) SSENB SSENA SREF Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-27 (Rev. 1.2)
  • Page 336 (T16 Ch.3 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x548c T16_3INTE 15–8 – 0x00 – – (T16 Ch.3 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-28 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 337 (ADC12A Ch.0 AD6OVIE Interrupt Enable AD5OVIE Register) AD4OVIE AD3OVIE AD2OVIE AD1OVIE AD0OVIE AD7CIE AD6CIE AD5CIE AD4CIE AD3CIE AD2CIE AD1CIE AD0CIE 0x54ac ADC12_0AD0D 15–0 AD0D[15:0] 0x0000 – (ADC12A Ch.0 Result Register 0) Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-A-29 (Rev. 1.2)

  • Page 338: 0X54C0-0X54C2 Temperature Sensor/Reference Voltage Generator (Tsrvr)

    Generator Control 1–0 VREFAMD[1:0] Register) 0xffff90 Debugger (DBG) Address Register name Bit name Initial Reset Remarks 0xffff90 DBRAM 31–24 – 0x00 – – (Debug RAM Base 23–0 DBRAM[23:0] 0x00 Register) 07c0 Seiko Epson Corporation AP-A-30 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 339: Appendix B Power Saving

    • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-B-1 (Rev. 1.2)

  • Page 340: Other Power Saving Methods

    • Setting the LCD voltage regulator into heavy load protection mode (LCD32PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 341: Appendix C Mounting Precautions

    ± 1 V. The C should be placed as close to the V pin as possible and use a sufficiently thick wiring pattern that allows current of several tens of mA to flow. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-C-1 (Rev. 1.2)

  • Page 342: Power Supply Circuit

    In this case, C can be omitted by connecting between the V and V pins directly. When these pins are not short-circuited, is required even if super economy mode is not used. Seiko Epson Corporation AP-C-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)
  • Page 343 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-C-3 (Rev. 1.2)

  • Page 344: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-D-1 (Rev. 1.2)
  • Page 345 The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation AP-D-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 346: Appendix E Initialization Routine

    %r1, 0x41b0 ; FLASHC register address ; Flash read wait cycle Xld.a %r0, 0x00 ; 0x00 = No wait ...(5) ld.b [%r1], %r0 ; [0x41b0] <= 0x00 ; ===== Main routine ========================================= Seiko Epson Corporation S1C17W34/W35/W36 TECHNICAL MANUAL AP-E-1 (Rev. 1.2)

  • Page 347: Interrupt Handler

    “intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17W34/W35/W36 TECHNICAL MANUAL (Rev. 1.2)

  • Page 348: Revision History

    Contents 413237900 New establishment 413237901 1-2, 1-3, ADIN07 of the A/D converter and the temperature sensor/reference voltage generator became available 4-8, 20-1, in the S1C17W34/W35. 21-1, AP-A-30 413237902 1-2 to 3 1.1 Features Modified Table 1.1. Power supply voltage: V operating voltage for Flash programming 1.8 V/2.7 V →...
  • Page 349 REVISION HISTORY Code No. Page Contents 413237902 10-3 10.4.1 SVD Control Starting detection Corrected Step 4. 4..- Set the SVDINTE.SVDIE bit to 1. 14-7 to 8 14.4.3 Data Reception in Master Mode Data receiving procedure Added Step 1. (The old step numbers were carried down in order.) 1.
  • Page 350 REVISION HISTORY Code No. Page Contents 413237902 23-3 23.3 Current Consumption Current consumption-frequency characteristic in RUN mode (OSC3 operation) The graph was replaced. 23-4 23.4 System Reset Controller (SRC) Characteristics Reset hold circuit characteristics Modified the characteristics table. : Min. = 0.5 ms, Max. = 0.9 ms RSTR 23-7 23.6 Flash Memory Characteristics...
  • Page 351 Fax: +86-10-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Phone: +49-89-14005-0 Fax: +49-89-14005-110 Epson Taiwan Technology & Trading Ltd. 15F, No.100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd. 1 HarbourFront Place,...

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