Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
10.1.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register's I flag, IPL, and each interrupt control register's ILVL2 to ILVL0 bits to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each
interrupt control register.
Figure 10.3 shows the interrupt control registers.
Rev.0.91
2003 Sep 08
page 52 of 184
10.1 Interrupt Overview