Chapter 14. A-D Converter - Renesas M16C FAMILY Hardware Manual

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
14. A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. The analog inputs share the pins with P0
using these pins, make sure the corresponding port direction bits are set to "0" (input mode).
When not using the A-D converter, set the VCUT bit to "0" (Vref unconnected), so that no current will flow
from the V pin into the resistor ladder, helping to reduce the power consumption of the chip.
REF
The result of A-D conversion is stored in the AD register.
Table 14.1 shows the performance of the A-D converter. Figure 14.1 shows a block diagram of the A-D
converter, and Figures 14.2 and 14.3 show the A-D converter-related registers.
Table 14.1 Performance of A-D converter
Item
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage
Operating clock φ
AD 2
Resolution
Integral nonlinearity error
Operating modes
Analog input pins
A-D conversion start condition ADST bit in ADCON0 register is set to "1" (A-D conversion starts)
Conversion speed per pin • Without sample and hold function
Notes:
1. Does not depend on use of sample and hold function.
2. The frequency of φ
When Vcc is less than 4.2V, φ
Without sample and hold function, the φ
With the sample and hold function, the φ
3. In repeat mode, only 8-bit mode can be used.
Rev.0.91 2003 Sep 08
1
0V to Vref
AV = 5V f
CC AD
AV = 3V divide-by-2 of f
CC
8-bit or 10-bit (selectable)
AVcc = Vref = 5V
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVcc = Vref = 3.3 V
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
One-shot mode and repeat mode
12 pins (AN to AN
0
8-bit resolution: 49 φ
• With sample and hold function
8-bit resolution: 28 φ
must be 10 MHz or less.
AD
must be f
AD
AD
AD
page 123 of 184
to P0
0
Performance
, divide-by-2 of f , divide-by-4 of f
AD
, divide-by-4 of f
AD
3
)
11
cycles, 10-bit resolution: 59 φ
AD
cycles, 10-bit resolution: 33 φ
AD
/2 or less by dividing f
AD
frequency should be 250 kHz or more.
frequency should be 1 MHz or more.
14. A-D Converter
and P1 to P1 . Therefore, when
7 0 3
AD
AD
cycles
AD
cycles
AD
.
AD