Renesas M16C FAMILY Hardware Manual page 64

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
• I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to "1" (enabled) enables the
maskable interrupt. Setting the I flag to "0" (disabled) disables all maskable interrupts.
• IR Bit
The IR bit is set to "1" (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit
is cleared to "0" (= interrupt not requested).
The IR bit can be cleared to "0" in a program. Note that do not write "1" to this bit.
• ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect
one another.
Table 10.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 bits
000 Level 0 (interrupt disabled)
2
Level 1
001
2
010 Level 2
2
011 Level 3
2
100 Level 4
2
101 Level 5
2
110 Level 6
2
111 Level 7
2
Rev.0.91 2003 Sep 08
Interrupt priority Priority
level order
Lowest
Highest
page 54 of 184
Table 10.4 Interrupt Priority Levels Enabled
by IPL
IPL Enabled interrupt priority levels
000
2 Interrupt levels 1 and above are enabled
001
Interrupt levels 2 and above are enabled
2
010
2 Interrupt levels 3 and above are enabled
011
2 Interrupt levels 4 and above are enabled
100
2 Interrupt levels 5 and above are enabled
101
2 Interrupt levels 6 and above are enabled
110
2 Interrupt levels 7 and above are enabled
111
2 All maskable interrupts are disabled
10.1 Interrupt Overview