Sample And Hold - Renesas M16C FAMILY Hardware Manual

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group

14.3 Sample and Hold

If the SMP bit in the ADCON2 register is set to "1" (with sample-and-hold), the conversion speed per
pin is increased to 28
and-hold is effective in all operation modes. Select whether or not to use the sample-and-hold function
before starting A-D conversion.
Rev.0.91 2003 Sep 08
cycles for 8-bit resolution or 33
ØAD
page 131 of 184
14. Sample and Hold mode
cycles for 10-bit resolution. Sample-
ØAD