Renesas M16C FAMILY Hardware Manual page 100

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Notes:
1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is "0" (one-edge).
2. The INOSGT bit must be set to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register
are set.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Notes:
1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count
source.
Figure 12.21 PUM Register and TCSS Register
Rev.0.91 2003 Sep 08
Symbol
0 0 PUM
Bit symbol Bit name
Reserved bit
(b3-b0)
TYOPL
Timer Y output level
latch
TZOPL Timer Z output level
latch
INT0 pin one-shot
INOSTG
trigger control bit
INT0 pin one-shot trigger
INOSEG
polarity select bit
Symbol
TCSS
Bit symbol
Timer X count source
TXCK0
select bit
TXCK1
TYCK0
Timer Y count source
select bit
TYCK1
Timer Z count source
TZCK0
select bit
TZCK1
Reserved bit
(b7-b6)
page 90 of 184
Address After reset
0084 00
16 16
Must set to "0"
Function varies depending on the operation mode
Function varies depending on the operation mode
0 : INT0 pin one-shot trigger invalid
2
1 : INT0 pin one-shot trigger valid
(Timer Z)
0 : Edge trigger at falling edge
1
1 : Edge trigger at rising edge
(Timer Z)
Address After reset
008E 00
16 16
Bit name
b1 b0
0 0 : f
1 1
0 1 : f
8
1 0 : f
32
1 1 : f
2
b3 b2
0 0 : f
1
1
0 1 : f
8
1 0 : f
RING
1 1 : Selects input from CNTR
b5 b4
0 0 : f
1
1
0 1 : f
8
1 0 : Selects Timer Y underflow
1 1 : f
2
Must be set to "0"
12.3 Timer (Timer Z)
Function
Function
pin
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW