Renesas M16C FAMILY Hardware Manual page 36

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Voltage detection circuit
VC27
V +
CC1
Noise
canceller
V
REF
-
(Canceller width: 200 ns)
Voltage detection signal
is "H" when VC27 bit= 0
(disabled)
Watchdog timer block
Watchdog timer
underflow signal
D40, D41, D42, D43, DF0, DF1, D46, D47: Bits in D4INT register
VC13: Bit in VCR1 register
VC27: Bit in VCR2 register
Figure 5.13 Operation Detection Interrupt Generation Block
VCC
VC13 bit
2
Output of digital filter
D42 bit
Voltage detection
interrupt signal
Notes:
1. D40 is "1"(voltage detection interrupt enabled).
2. Output of the digital filter shown in Figure 5.11
Figure 5.14 Voltage Detection Interrupt Generation Circuit Operation Example
Rev.0.91 2003 Sep 08
Voltage detection interrupt generation circuit
f
RING-S
1/2 1/2
VC13
Noise rejection
Voltage circuit
detection
signal
CM10
D43
D47
This bit is set to "0"(not detected) by writing a "0" in a program.
CM02: Bit in CM0 register
CM10: Bit in CM1 register
sampling
page 26 of 184
DF1 to DF0
=00
2
D42 bit is set to "0"(not detected)
=01
2
by writing a "0" in a program.
=10
2
When VC27 bit is set to "0" (
=11 voltage detection circuit
2
1/2
disabled), D42 bit is set to "0" .
Digital
filter D42
D41
D40
sampling
No voltage detection interrupt
signals are generated when D42 bit
is "H".
Set D42 bit to "0"
in a program (not
detected)
D42: Bit in D4INT register
VC13: Bit in VCR1 register
5.4 Voltage Detection Circuit
Watchdog
timer interrupt
signal
Voltage
detection
interrupt signal
Oscillation stop
detection
interrupt signal
Hardware reset 2
D46
sampling sampling
Set D42 bit to "0"
in a program (not
detected)
Non-maskable
interrupt signal