Renesas M16C FAMILY Hardware Manual page 25

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
b19
Content of addresses 0FFFE
b15
IPL
Figure 5.1 CPU Register Status After Reset
Internal ring
oscillation
More than 20 cycles are needed
RESET
CPU clock
Address
(Internal address
signal)
Figure 5.2 Reset Sequence
Rev.0.91 2003 Sep 08
b15
0000
0000
0000
0000
0000
0000
0000
00000
16
b15
0000
0000
0000
b15
0000
b8 b7
U I O
CPU clock: 28cycles
page 15 of 184
b0
16
16
16
16
16
16
16
b0
to 0FFFC
16 16
b0
16
16
16
b0
16
b0
B S Z D C
0FFFE
0FFFC
16
16
0FFFD
16
5.1 Hardware Reset
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB)
Interrupt table register(INTB)
Program counter(PC)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Flag register(FLG)
Content of reset vector