Chapter 11. Watchdog Timer - Renesas M16C FAMILY Hardware Manual

Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
11. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit in the PM1 register. The PM12 bit can only be set to "1" (reset). Once this bit is set to "1", it
cannot be set to "0" (watchdog timer interrupt) in a program. Refer to Section 5.1.5, "Watchdog Timer
Reset" for details.
The divide-by-N value for the prescaler can be chosen to be 16 or 128 with the WDC7 bit in the WDC
register. The period of watchdog timer can be calculated as given below. The period of watchdog timer is,
however, subject to an error due to the prescaler.
Watchdog timer period =
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register. After that, the watchdog timer is initialized by
writing to the WDTR register and the counting continues.
In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from
the held value when the modes or state are released.
Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timer-
related registers.
CPU clock
Write to WDTS register
RESET
Figure 11.1 Watchdog Timer Block Diagram
Rev.0.91 2003 Sep 08
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Prescaler
WDC7 = 0
1/16
WDC7 = 1
1/128
page 68 of 184
CPU clock
Watchdog timer
Set to
"7FFF "
16
11. Watchdog Timer
PM12 = 0
Watchdog timer
interrupt request
PM12 = 1
Watchdog
timer Reset