Renesas M16C FAMILY Hardware Manual page 138

16-bit single-chip microcomputer
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Notes:
1. If the ADCON0 register is rewritten during A-D conversion, the conversion result is indeterminate.
2. When changing A-D operation mode, set analog input pin again.
3. This bit is valid when the CKS1 bit in the ADCON1 register is set to "0".
4. The analog input pin can be selected by a combination of the CH2 to CH0 bits and ADGSEL0 bit as follows:
CH2 to CH0
000
2
001
2
010
2
011
2
100
2
101
2
110
2
111
2
A-D control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
1
0
Notes:
1. If the ADCON1 register is rewritten during A-D conversion, the conversion result is indeterminate.
2. The φ
frequency must be 10 MHz or less.
AD
3. If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting A-D
conversion.
Figure 14.4 ADCON0 Register and ADCON1 Registers in One-shot Mode
Rev.0.91
2003 Sep 08
Symbol
ADCON0
Bit symbol
CH0
Analog input pin select bit
CH1
CH2
A-D operation mode
MD
select bit
A-D input group select bit
ADGSEL0
Reserved bit
(b5)
A-D conversion start flag
ADST
Frequency select bit 0
CKS0
ADGSEL0=0
ADGSEL0=1
AN
0
Avoid these
AN
1
settings
AN
2
AN
3
AN
AN
4
8
AN
5
AN
9
AN
AN
6
10
AN
AN
7
11
1
Symbol
ADCON1
0
0
Bit symbol
Bit name
Reserved bit
(b2-b0)
8/10-bit mode select
BITS
bit
Frequency select bit 1
CKS1
Vref connect bit
VCUT
Reserved bit
(b6-b7)
page 128 of 184
Address
After reset
00D6
00000XXX
16
Bit name
2
See Note 4
0 : One-shot mode
2
0: Port P0 group selected (AN
4
1: Port P1 group selected (AN
Must set to "0"
0 : A-D conversion disabled
1 : A-D conversion started
3
0 : f
/4 is selected
AD
1 : f
/2 is selected
AD
Address
After reset
00D7
00
16
16
Must set to "0"
0 : 8-bit mode
1 : 10-bit mode
2
0 : CKS0 bit in ADCON0 register is valid
1 : f
is selected
AD
1 : Vref connected
3
Must set to "0"
14. One-shot mode
2
Function
to AN
)
0
7
to AN
)
8
11
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

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