Renesas M16C FAMILY Hardware Manual page 125

Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register Bit
U0TB 0 to 7
U0RB 0 to 7
OER
U0BRG 0 to 7
U0MR SMD2 to SMD0
CKDIR
U0C0 CLK1 to CLK0
TXEPT
NCH
CKPOL
UFORM
U0C1 TE
TI
RE
RI
UCON U0IRS
U0RRM
TXDISEL
TXDIEN
Notes:
1. Not all register bits are described above. Set those bits to "0" when writing to the registers in clock
synchronous serial I/O mode.
Table 13.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that
for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin
outputs an "H". (If the Nch bit is set to "1", this pin is in a high-impedance state.)
Table 13.3 Pin Functions
Pin name
TxD
0
Serial data output
(P1 )
4
Serial data input
RxD
0
(P1 )
5
CLK Transfer clock output
0
(P1 )
6
Transfer clock input
Rev.0.91 2003 Sep 08
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to "001 "
2
Select the internal clock or external clock
Select the count source for the U0BRG register
Transmit register empty flag
Select TxD0 pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to "1" to enable transmission/reception
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Select the source of UART0 transmit interrupt
Set this bit to "1" to use continuous receive mode
Set to "0"
Set to "0"
Function
(Outputs dummy data when performing reception only)
PD1 register PD1_5 bit=0
(P1 can be used as an input port when performing transmission only)
5
U0MR register CKDIR bit=0
U0MR register CKDIR bit=1
PD1 register PD1_6 bit=0
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13.1 Clock Synchronous Serial I/O Mode
Function
Method of selection