Renesas M16C FAMILY Hardware Manual page 134

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
f
AD
VCUT=0
AV
SS
VCUT=1
V
REF
P0 /AN
7 0
P0 /AN
6 1
P0 /AN
5 2
P0 /AN
4 3
P0 /AN
3 4
P0 /AN
2 5
P0 /AN
1 6
P0 /AN
0 7
P1 /AN
0 8
P1 /AN
1 9
P1 /AN
2 10
P1 /AN
3 11
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register
CKS1, VCUT: Bits in ADCON1 register
Figure 14.1 A-D Converter Block Diagram
Rev.0.91 2003 Sep 08
1/2 1/2
Resistor ladder
Successive conversion register
AD register
Data bus
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
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CKS0=1
CKS0=0
ADCON0
2
2
2
2
2
2
2
2
2
2
2
2
14. A-D Converter
CKS1=1
A-D conversion rate
CKS1=0
selection
V
ref
Decoder
Comparator
V
IN
ADGSEL0=0
ADGSEL0=1
φ
AD