Renesas M16C FAMILY Hardware Manual page 67

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
• Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved.
Figure 10.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine.
Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
m – 4
m – 3
m – 2
m – 1
m
m + 1
Stack status before interrupt request
is acknowledged
Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request
The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving
registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP
indicated by the U flag. Otherwise, it is the ISP.
Address
[SP] – 5
[SP] – 4
[SP] – 3
[SP] – 2
[SP] – 1
[SP]
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 10.7 Operation of Saving Register
Rev.0.91 2003 Sep 08
Stack
LSB
[SP]
SPvalue before
Content of previous stack
interrupt occurs
Content of previous stack
Stack
PC
L
PC
M
FLG
L
FLG PC
H H
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Address
MSB
m – 4
m – 3
m – 2
m – 1
FLG
H
m
Content of previous stack
Content of previous stack
m + 1
Stack status after interrupt request
is acknowledged
Sequence in which order
registers are saved
(3)
(4)
Saved, 8 bits at a time
(1)
(2)
Finished saving registers
in four operations.
10.1 Interrupt Overview
Stack
LSB
[SP]
New SP value
PC
L
PC
M
FLG
L
PC
H