Int3 Interrupt - Renesas M16C FAMILY Hardware Manual

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
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10.2.4 INT3 Interrupt

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INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should be se to "0"
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(INT3). The INT3 input has a digital filter which can be sampled by one of three sampling clocks. The
sampling clock is selected using the TCC11 to TCC10 bits in the TCC1 register. The IR bit in the
INT3IC register is set to "1" (interrupt requested) when the sampled input level matches three times.
The P3_3 bit in the P3 register indicates the previous value before filtering regardless of values set in
the TCC11 to TCC10 bits.
When setting the TCC07 bit to "1" (f
bit in the INT3IC register is set to "1" (interrupt requested) every f
f clock cycle.
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Figure 10.14 shows the TCC0 and TCC1 registers.
Rev.0.91 2003 Sep 08
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page 63 of 184
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), INT3 interrupts are triggered by f
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10.2 INT Interrupt
clock. The IR
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clock cycle or every half