Renesas M16C FAMILY Hardware Manual page 165

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Notes:
1. To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no
interrupts will occur before writing "1" after writing "0".
The FMR01 and FMR11 bits both are set to "0" by setting the FMR01 bit to "0".
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Notes:
1. To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before
writing "1" after writing "0".
2. This bit is valid only when the FMR40 bit is set to "1" (valid) and can only be written before ending an
erase after issuing an erase command. Other than this period, this bit is set to "1".
In EW0 mode, this bit can be set to "0" and "1" by program.
In EW1 mode, this bit is automatically set to "1" if a maskable interrupt occurs during an erase operation
while the FMR40 bit is set to "1". This bit can not be set to "1" by program. (Can be set to "0".)
Figure 17.3-2 FMR1 Register and FMR4 Register
Rev.0.91 2003 Sep 08
Symbol
FMR1
Bit symbol
Reserved bit
(b0)
FMR11 EW1 mode select bit
Reserved bit
(b3-b2)
Reserved bit
(b5-b4)
Nothing is assigned.
(b6)
When write, set to "0". When read, its content is indeterminate.
Reserved bit
(b7)
Symbol
FMR4
Bit symbol
Erase-suspend function
FMR40
enable bit
Erase-suspend request bit
FMR41
Reserved bit
(b5-b2)
Erase status
FMR46
Reserved bit
(b7)
page 155 of 184
Address After reset
01B5 0100XX0X
16
Bit name
When read, its content is
indeterminate.
1
0: EW0 mode
1: EW1 mode
When read, its content is
indeterminate.
Must always be set to "0"
Must set to "0"
Address After reset
01B3 0100000X
16
Bit name
0: Invalid
1 1: Valid
2 0: Erase restart
1: Suspend request
Should set to "0"
0: Auto-erase active
1: Auto-erase inactive (erase-suspend
mode)
Should set to "0"
17.4 CPU Rewrite Mode
2
Function
2
Function
RW
RO
RW
RO
RW
RO
RW
RW
RW
RW
RO
RO
RW