Chapter 9. Bus Control - Renesas M16C FAMILY Hardware Manual

Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
9. Bus
During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for
access space.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16
bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access
space.
Table 9.1 Bus Cycles for Access Space
Access space
SFR 2 CPU clock cycles
ROM/RAM 1 CPU clock cycles
Table 9.2 Access Unit and Bus Operation
Space
Even address
CPU clock
byte access
Add address
CPU clock
byte access
Even address
CPU clock
word access
Address
Data
CPU clock
Add address
word access
Rev.0.91 2003 Sep 08
Bus cycle
SFR
Address Even
Data
Address
Odd
Data
Even
Data
Address
Odd
Data
Data
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CPU clock
Address
Data
Data
CPU clock
Address
Data
Data
CPU clock
Address
Even+1
Data
Data
CPU clock
Odd+1
Address
Data
Data
ROM/RAM
Even
Data
Odd
Data
Even Even+1
Data Data
Odd Odd+1
Data
Data
9. Bus