Renesas M16C FAMILY Hardware Manual page 32

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Voltage detection interrupt register
b 7 b 6 b5 b 4 b 3 b 2
N o t e s :
1 . S e t t h e P R C 3 b i t i n t h e P R C R r e g i s t e r t o " 1 " ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . I f t h e v o l t a g e d e t e c t i o n i n t e r r u p t n e e d s t o b e u s e d t o g e t o u t o f s t o p m o d e a g a i n a f t e r o n c e u s e d f o r t h a t
p u r p o s e , r e s e t t h e D 4 1 b i t b y w r i t i n g a " 0 " a n d t h e n a " 1 " .
3. V a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o " 1 " ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) .
4 . I f t h e V C 2 7 b i t i s s e t t o " 0 " ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) , t h e D 4 2 a n d D 4 3 b i t s a r e s e t t o " 0 " ( n o t d e t e c t e d ) .
5 . T h i s b i t i s s e t t o " 0 " b y w r i t i n g a " 0 " i n a p r o g r a m . ( w r i t i n g a " 1 " h a s n o e f f e c t . )
6 . V a l i d w h e n t h e D 4 0 b i t i s s e t t o " 1 " ( v o l t a g e d e t e c t i o n i n t e r r u p t e n a b l e d ) .
7 . T h e D 4 0 b i t i s v a l i d w h e n t h e V C 2 7 b i t i n t h e V C R 2 r e g i s t e r i s s e t t o " 1 " ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) .
W h e n s e t t i n g t h e D 4 0 b i t t o " 1 " , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d .
( 1 ) S e t t h e V C 2 7 b i t " 1 " .
( 2 ) W a i t f o r t d ( E - A ) u n t i l t h e d e t e c t e r c i r c u i t o p e r a t e s .
( 3 ) W a i t f o r t h e s a m p l i n g t i m e ( t h e s a m p l i n g c l o c k w h i c h i s s e l e c t e d i n t h e D F 0 b i t t o D F 1 b i t t i m e s 4 c y c l e s . )
( 4 ) S e t t h e D 4 0 b i t t o " 1 " .
( 5 ) S e t t h e C M 1 4 b i t i n t h e C M 1 r e g i s t e r t o " 0 " ( l o w - s p e e d r i n g o s c i l l a t o r o n ) .
8 . V a l i d w h e n t h e D 4 1 b i t i s s e t t o " 1 " ( e n a b l e ) .
9 . T h e D 4 6 b i t c a n b e s e l e c t e d .
1 0 . T h e s o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o n o t a f f e c t t h i s r e g i s t e r .
Figure 5.9 D4INT Register
Rev.0.91 2003 Sep 08
1
b 1 b 0
S y m b o l
D 4 I N T
B i t s y m b o l
Voltage detection interrupt
D40
enable bit
STOP mode deactivation
D41
control bit
Voltage change detection
D42
3, 4, 5
flag
D43 WDT overflow detect flag
Sampling clock select bit
DF0
DF1
Voltage monitor mode select
D46
6
bit
D47
Stop mode exiting condition
select bit
page 22 of 184
A d d r e s s A f t e r r e s e t
0 0 1 F R e s e t i n p u t : 0 0
1 6
R E S E T p i n = " H " r e t a i n i n g : 0 1 0 0 0 0 0 1
B i t n a m e
Disable
0 :
7
Enable
1 :
0 : D i s a b l e ( d o n o t u s e t h e v o l t a g e
d e t e c t i o n i n t e r r u p t t o g e t o u t o f
2
s t o p m o d e )
1 : E n a b l e ( u s e t h e v o l t a g e
d e t e c t i o n i n t e r r u p t t o g e t o u t o f
s t o p m o d e )
0: Not detected
1: Vdet passing detection
0 : N o t d e t e c t e d ( f l a g c l e a r )
3, 4
1 : D e t e c t e d
b5b 4
00 : f
01 : f
10 : f
11 : f
0: Voltage detection interrupt
request is generated when
passing through Vdet
1: Hardware reset 2 when
passing through Vdet
I n s t o p m o d e , v o l t a g e d e t e c t i o n
i n t e r r u p t r e q u e s t i s g e n e r a t e d
8
o r h a r d w a r e r e s e t 2
w h e n V c c p a s s e s V d e t
0 : O v e r V d e t
1 : B e l o w V d e t
5.4 Voltage Detection Circuit
1 0
1 6
2
RW
F u n c t i o n
RW
RW
RW
RW
R W
divided by 1
RING-S
divided by 2
RING-S
divided by 4
RING-S
divided by 8
RING-S
RW
R W
9
RW