Renesas M16C FAMILY Hardware Manual page 122

Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
UARTi transmit/receive mode register (i=0, 1)
b7 b6 b5 b4 b3 b2 b1
0
Notes:
1. Must set the P1_6 bit in the PD1 register to "0" (input).
2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: "000
3. Must set the CKDIR bit to "0" (internal clock) in UART1.
UARTi transmit/receive control register 0 (i=0, 1)
b7 b6 b5 b4 b3 b2 b1
0
Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers
Rev.0.91 2003 Sep 08
b0
Symbol
U0MR
U1MR
Bit
Bit name
symbol
SMD0
Serial I/O mode
2
select bit
SMD1
SMD2
CKDIR Internal/external clock
3
select bit
STPS
Stop bit length select bit
PRY
Odd/even parity select bit
PRYE
Parity enable bit
Reserved bit
(b7)
b0
Symbol
U0C0
U1C0
Bit
Bit name
symbol
CLK0 BRG count source
select bit
CLK1
Reserved bit
(b2)
TXEPT Transmit register empty
flag
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
(b4)
Data output select bit
NCH
CKPOL CLK polarity select bit
UFORM Transfer format select bit
page 112 of 184
Address After reset
00A0 00
16 16
00A8 00
16 16
b2 b1 b0
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
0 : Internal clock
1
1 : External clock
0 : One stop bit
1 : Two stop bits
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Must set to "0"
Address After reset
00A4 08
16 16
00AC 08
16 16
b1 b0
0 0 : f is selected
1SIO
0 1 : f is selected
8SIO
1 0 : f is selected
32SIO
1 1 : Avoid this setting
Must set to "0"
0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
(transmission completed)
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
0 : LSB first
1 : MSB first
Function
", "100 ", "101 ", or "110 ".
2 2 2 2
Function
13. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW