Chapter 13. Serial I/O - Renesas M16C FAMILY Hardware Manual

Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
13. Serial I/O
Serial I/O is configured with two channels: UART0 to UART1. UART0 and UART1 each have an exclusive
timer to generate a transfer clock, so they operate independently of each other.
Figure 13.1 shows a block diagram of UARTi (i=0, 1). Figure 13.2 shows a block diagram of the UARTi
transmit/receive.
UART0 has two modes: clock synchronous serial I/O mode, and clock asynchronous serial I/O mode (UART
mode).
UART1 has only one mode, clock asynchronous serial I/O mode (UART mode).
Figures 13.3 to 13.5 show the UARTi-related registers.
(UART0)
RxD
0
CLK to CLK =00
1 0 2
f
1SIO
Internal
=01
2
f
8SIO
=10
2
f
32SIO
External
Clock synchronous type
(when internal clock is selected)
CLK
polarity
CLK
0
reversing
circuit
(UART1)
TXD1EN
RxD
1
CLK to CLK =00
1 0 2
f
1SIO
=01
2 Internal
f
8SIO
=10
2
f
32SIO
Figure 13.1 UARTi (i=0, 1) Block Diagram
Rev.0.91 2003 Sep 08
Main clock or ring oscillator clock
UART reception
1/16
Clock synchronous
type
U0BRG register
UART transmission
1/16
1/(n0+1)
Clock synchronous
type
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is selected)
UART reception
1/16
U1BRG
register
UART transmission
1/(n1+1) 1/16
page 109 of 184
f
1SIO
1/8
f
8SIO
1/4
f
32SIO
Receive
Reception clock
control circuit
Transmit
clock
Transmission control
circuit
CKDIR=0
CKDIR=1
Reception
control circuit
Reception
control circuit
Transmission
control circuit
Transmission
control circuit
13. Serial I/O 13. Serial I/O
TxD
0
Transmit/
receive
unit
TxD
10
TXD1SEL=1
Transmit/
TxD
11
receive
unit
TXD1SEL=0
To P0
0