Renesas M16C FAMILY Hardware Manual page 126

Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
• Example of transmit timing (when internal clock is selected)
Transfer clock
"1"
U0C1 register
TE bit
"0"
U0C1 register
"1"
TI bit
"0"
CLK
0
TxD
0
U0C0 register
"1"
TXEPT bit
"0"
S0TIC register
"1"
IR bit
"0"
The above timing diagram applies to the case where the register bits are set as follows:
• U0MR register CKDIR bit = 0 (internal clock)
• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• U0IRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
• Example of receive timing (when external clock is selected)
"1"
U0C1 register
"0"
RE bit
"1"
U0C1 register
"0"
TE bit
"1"
U0C1 register
TI bit
"0"
CLK
0
RxD
0
"1"
U0C1 register
RI bit
"0"
"1"
S0RIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set as follows:
• U0MR register CKDIR bit = 1 (external clock)
• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
Make sure the following conditions are met when input to the CLK0 pin before receiving data is high:
• U0C1 register TE bit = 1 (transmit enabled)
• U0C1 register RE bit = 1 (receive enabled)
• Write dummy data to the U0TB register
f : frequency of external clock
EXT
Figure 13.6 Transmit and Receive Operation
Rev.0.91 2003 Sep 08
Tc
Write data to U0TB register
Transferred from U0TB register to UART0 transmit register
T
CLK
D D D D D D D
0 1 2 3 4 5 6
Write dummy data to U0TB register
1 / f
EXT
Receive data is taken in
D D D D D D
0 1 2 3 4 5
Transferred from UART0 receive register
to U0RB register
Set to "0" when interrupt request is accepted, or set by a program
data taken in at the rising edge of the transfer clock)
page 116 of 184
D D
D D D D D D D
7
0 1 2 3 4 5 6
Set to "0" when interrupt request is accepted, or set by a program
Tc = T = 2(n + 1) / fi
CLK
fi: frequency of U0BRG count source (f
n: value set to U0BRG register
Transferred from U0TB register to UART0 transmit register
D D D D D D D
6 7 0 1 2 3 4
Read out from U0RB register
13.1 Clock Synchronous Serial I/O Mode
Stopped pulsing because the TE bit = 0
D D D D D D
7
0 1 2 3 4
, f , f
1SIO 8SIO
D
5
D
D
7
5 6
)
32SIO