Renesas M16C FAMILY Hardware Manual page 114

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. Input is recognized only when the same value from INT3 pin is sampled three times in succession.
2. The TCC00 bit in the TCC0 register should be set to "0" (count stop) when rewriting the TCC13 bit.
3. The TCC12 and TCC14 to TCC17 should be set to "0" when the TCC13 bit is "0" (input capture mode).
Timer C output control register
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. Invalid when the TCC13 bit in the TCC1 register is set to "0" (input capture mode).
Figure 12.32 TCC1 Register and TCOUT Register
Rev.0.91 2003 Sep 08
Symbol Address
TCC1 009B
Bit symbol
Bit name
INT3 input filter select bit
TCC10
TCC11
Timer C counter reload
TCC12
2, 3
select bit
Compare 0/Capture select
TCC13
bit
Compare 0 output mode
TCC14
3
select bit
TCC15
Compare 1 output mode
TCC16
3
select bit
TCC17
1
Symbol Address
TCOUT 00FF
Bit symbol
Bit name
CMP output enable bit 0
TCOUT0
CMP output enable bit 1
TCOUT1
CMP output enable bit 2
TCOUT2
CMP output enable bit 3
TCOUT3
TCOUT4 CMP output enable bit 4
CMP output enable bit 5
TCOUT5
CMP output reverse bit 0
TCOUT6
CMP output reverse bit 1
TCOUT7
page 104 of 184
After reset
00
16 16
Function
b1 b0
1
0 0: No filter
0 1: Filter with f sampling
1
1 0: Filter with f sampling
8
1 1: Filter with f sampling
32
0: No reload (free-run)
1: Set TC register to "0000
compare 1 match
0: Capture
(input capture mode)
1: Compare 0 output
(output compare mode)
b5 b4
0 0: CMP0 output remains unchanged
even when compare 0 signal
matched
0 1: CMP0 output is reversed when
compare 0 signal is matched
1 0: CMP0 output is set to low when
compare 0 signal is matched
1 1: CMP0 output is set to high when
compare 0 signal is matched
b7 b6
0 0: CMP1 output remains unchanged
even when compare 1 signal
matched
0 1: CMP1 output is reversed when
compare 1 signal is matched
1 0: CMP1 output is set to low when
compare 1 signal is matched
1 1: CMP1 output is set to high when
compare 1 signal is matched
After reset
00
16 16
Function
0: Disable CMP output from CMP0
1: Enable CMP output from CMP0
0: Disabe CMP output from CMP0
1: Enable CMP output from CMP0
0: Disable CMP output from CMP0
1: Enable CMP output from CMP0
0: Disable CMP output from CMP1
1: Enable CMP output from CMP1
0: Disable CMP output from CMP1
1: Enable CMP output from CMP1
0: Disable CMP output from CMP1
1: Enable CMP output from CMP1
0: Not reverse CMP output from
CMP0 to CMP0
0 2
1: Reverse CMP output from
CMP 0 to CMP0
0 2
0: Not reverse CMP output from
CMP1 to CMP1
0 2
1: Reverse CMP output from
CMP1 to CMP1
0 2
12.4 Timer (Timer C)
RW
RW
RW
RO
" at
16
2
RW
RW
RW
RW
0
RW
0
1
RW
1
2
RW
2
0
RW
0
1
RW
1
2
RW
2
RW
RW