Renesas M16C FAMILY Hardware Manual page 74

Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/11 Group
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Notes:
1. Change this bit when TCC00 bit is set to "0" (count stop).
2. The IR bit in the INT3IC may be set to "1" (interrupt requested) when the TCC03, TCC04, or TCC07 bit is rewritten.
Refer to the paragraph 19.2.5 "Changing Interrupt Source" in the Usage Notes Reference Book.
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Notes:
1. Input is recognized only when the same value from INT3 pin is sampled three times in succession.
2. The TCC00 bit in the TCC0 register should be set to "0" (count stop) when rewriting the TCC13 bit.
3. The TCC12 and TCC14 to TCC17 should be set to "0" when the TCC13 bit is "0" (input capture mode).
Figure 10.14 TCC0 Register and TCC1 Register
Rev.0.91 2003 Sep 08
Symbol
TCC0
Bit symbol
Timer C control bit
TCC00
Timer C count source select
TCC01
1
bit
TCC02
INT3 interrupt and capture
TCC03
polarity select bit
TCC04
Reserved bit
(b6-b5)
INT3 interrupt/capture input
TCC07
switching bit
Symbol
TCC1
Bit symbol
INT3 input filter select bit
TCC10
TCC11
Timer C counter reload
TCC12
select bit
Compare 0/Capture select
TCC13
bit
Compare 0 output mode
TCC14
select bit
TCC15
Compare 1 output mode
TCC16
select bit
TCC17
page 64 of 184
Address After reset
009A 00
16 16
Bit name
0 : Count stop
1 : Count start
b2 b1
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
RING
b4 b3
0 0 : Rising edge
1, 2
0 1 : Falling edge
1 0 : Both edges
1 1 : Avoid this setting
Must set to "0"
0 : INT3
1, 2
1 : f
RING128
Address After reset
009B 00
16 16
Bit name
b1 b0
1
0 0: No filter
0 1: Filter with f
1 0: Filter with f
1 1: Filter with f
0: No reload (free-run)
1: Set TC register to "0000
2, 3
compare 1 match
0: Capture
(input capture mode)
1: Compare 0 output
(output compare mode)
b5 b4
3
0 0: CMP0 output remains unchanged
even when compare 0 signal
matched
0 1: CMP0 output is reversed when
compare 0 signal is matched
1 0: CMP0 output is set to low when
compare 0 signal is matched
1 1: CMP0 output is set to high when
compare 0 signal is matched
b7 b6
3
0 0: CMP1 output remains unchanged
even when compare 1 signal
matched
0 1: CMP1 output is reversed when
compare 1 signal is matched
1 0: CMP1 output is set to low when
compare 1 signal is matched
1 1: CMP1 output is set to high when
compare 1 signal is matched
10.2 INT Interrupt
Function
RW
RW
RW
RW
-fast
RW
RW
RW
RW
Function
RW
RW
sampling
1
sampling
8
RW
sampling
32
RO
" at
16
2 RW
RW
RW
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