Chapter 9. Bus - Renesas M16C Series Hardware Manual

R8C/11 Group
9. Bus
During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for
access space.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16
bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access
space.
Table 9.1 Bus Cycles for Access Space
Access space
SFR/Data flash
Program ROM/RAM
Table 9.2 Access Unit and Bus Operation
Space
Even address
CPU clock
byte access
Odd address
CPU clock
byte access
Even address
CPU clock
word access
Address
Data
CPU clock
Odd address
word access
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
Bus cycle
2 CPU clock cycles
1 CPU clock cycles
SFR, Data flash
Address
Even
Data
Address
Odd
Data
Even
Data
Address
Odd
Data
Data
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CPU clock
Address
Data
Data
CPU clock
Address
Data
Data
CPU clock
Address
Even+1
Data
Data
CPU clock
Odd+1
Address
Data
Data
Program ROM/RAM
Even
Data
Odd
Data
Even Even+1
Data Data
Odd Odd+1
Data
Data
9. Bus