Configurable Logic Blocks - ABB REL650 series Technical Manual

1MRK 506 335-UUS A
13.4
13.4.1
13.4.1.1
Technical manual
ModeOutput1=Pulsed
Input 1
OR
ModeOutput2=Pulsed
Input 17
OR
ModeOutput3=Pulsed
ANSI11000290 V1 EN
Figure 260: Trip matrix internal logic
Output signals from TMAGGIO are typically connected to other logic blocks or directly
to output contacts in the IED. When used for direct tripping of the circuit breaker(s) the
pulse time delay shall be set to approximately 0.150 seconds in order to obtain satisfactory
minimum duration of the trip pulse to the circuit breaker trip coils.

Configurable logic blocks

Standard configurable logic blocks
Functionality
A number of logic blocks and timers are available for the user to adapt the configuration
to the specific application needs.
• OR function block. Each block has 6 inputs and two outputs where one is inverted.
On Delay Time 1
0 Off Delay Time 1
AND
On Delay Time 2
0
Off Delay Time 2
On Delay Time 3
OR
0
Off Delay Time 3
Section 13
PulseTime
t
AND
OR
AND
0
PulseTime
t
AND
OR
AND
0
PulseTime
t
AND
OR
AND
0
ANSI11000290-1-en.vsd
Logic
Output 1
Output 2
Output 3
541