Operation Principle - ABB REL650 series Technical Manual

1MRK 506 335-UUS A
10.1.6
Technical manual

Operation principle

Current circuit supervision CCSRDIF (87) compares the absolute value of the vectorial
sum of the three phase currents |ΣIphase| and the numerical value of the residual current
|Iref| from another current transformer set, see figure 155.
The FAIL output will be set to a logical one when the following criteria are fulfilled:
• The numerical value of the difference |ΣIphase| – |Iref| is higher than 80% of the
numerical value of the sum |ΣIphase| + |Iref|.
• The numerical value of the current |ΣIphase| – |Iref| is equal to or higher than the set
operate value IMinOp.
• No phase current has exceeded Pickup_Block during the last 10 ms.
• CCSRDIF (87) is enabled by setting Operation = Enabled.
The FAIL output remains activated 100 ms after the AND-gate resets when being
activated for more than 20 ms. If the FAIL lasts for more than 150 ms an ALARM will be
issued. In this case the FAIL and ALARM will remain activated 1 s after the AND-gate
resets. This prevents unwanted resetting of the blocking function when phase current
supervision element(s) operate, for example, during a fault.
I I
I
A
A
I I
B
B
I
I
C C
I
I
ref
ref
OPERATION
BLOCK
ANSI11000291 V1 EN
Figure 155: Simplified logic diagram for Current circuit supervision CCSRDIF (87)
The operate characteristic is percentage restrained, see figure 156.
Secondary system supervision
I>Pickup_Block
BLOCK
I>IMinOp
+
å
å
-
+ +
å
å
x
+ -
0,8
1,5 x I r
10 ms
OR
0
Section 10
FAIL
OR
AND
20-100 ms
0
ALARM
150 ms-1 s
0
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