Configurable Logic Blocks; Standard Configurable Logic Blocks; Functionality - ABB REG650 Technical Manual

1MRK 502 048-UEN A
13.3
13.3.1
13.3.1.1
Technical manual
ModeOutput1=Pulsed
Input 1
³1
ModeOutput2=Pulsed
Input 17
³1
ModeOutput3=Pulsed
IEC09000612 V2 EN
Figure 216: Trip matrix internal logic
Output signals from TMAGGIO are typically connected to other logic blocks or
directly to output contacts in the IED. When used for direct tripping of the circuit
breaker(s) the pulse time delay shall be set to approximately 0.150 seconds in order to
obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip coils.

Configurable logic blocks

Standard configurable logic blocks

Functionality

A number of logic blocks and timers are available for the user to adapt the
configuration to the specific application needs.
• OR function block. Each block has 6 inputs and two outputs where one is
inverted.
• INVERTER function blocks that inverts the input signal.
Ondelay
t
Ondelay
t
Ondelay
³1
t
Section 13
PulseTime
t
&
³1
Offdelay
&
t
PulseTime
t
&
³1
Offdelay
&
t
PulseTime
t
&
³1
Offdelay
&
t
IEC09000612_2_en.vsd
Logic
Output 1
Output 2
Output 3
439