Freescale Semiconductor MSC8144E Reference Manual

Quad core media signal processor

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MSC8144E Reference Manual

Quad Core Media Signal Processor

MSC8144ERM

Rev 3, July 2009

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Page 1 MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3, July 2009...
Page 2 Technical Information Center purpose, nor does Freescale Semiconductor assume any liability arising out of the Schatzbogen 7 application or use of any product or circuit, and specifically disclaims any and all 81829 Muenchen, Germany liability, including without limitation consequential or incidental damages.
Page 3 Overview SC3400 Core Overview External Signals Chip-Level Arbitration and Switching System (CLASS) Reset Boot Program Clocks General Configuration Registers Memory Map MSC8144 SC3400 DSP Subsystem Internal Memory Subsystem DDR-SDRAM Controller Interrupt Processing Direct Memory Access (DMA) Controller Serial RapidIO™ Controller RapidIO Interface Dedicated DMA Controller QUICC Engine™...
Page 4 Overview SC3400 Core Overview External Signals Chip-Level Arbitration and Switching System (CLASS) Reset Boot Program Clocks General Configuration Registers Memory Map MSC8144 SC3400 DSP Subsystem Internal Memory Subsystem DDR-SDRAM Controller Interrupt Processing Direct Memory Access (DMA) Controller Serial RapidIO™ Controller RapidIO Interface Dedicated DMA Controller QUICC Engine™...
Page 5: Table Of Contents
Other MSC8144E Documentation ........
Page 6 Additional Programming Considerations......2-22 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 7 Hard Reset ........... . 4-12 MSC8144E Reference Manual, Rev. 3...
Page 8 Reset Configuration ..........5-7 MSC8144E Reference Manual, Rev. 3...
Page 9 Serial RapidIO Interconnect ........6-19 MSC8144E Reference Manual, Rev. 3...
Page 10 General Interrupt Register 1 (GIR1) ....... . 8-14 MSC8144E Reference Manual, Rev. 3...
Page 11 10.9.6.8 Transition from STOP to Execution state ......10-13 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 12 L2 ICache Valid State Register (L2IC_VALID) ..... 11-32 11.8.7 L2 ICache Debug Data Register (L2IC_DBG_DATA) ....11-32 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 13 (DDR_SDRAM_INTERVAL) ........12-49 MSC8144E Reference Manual, Rev. 3...
Page 14 General Configuration Block ........13-3 MSC8144E Reference Manual, Rev. 3...
Page 15 Nonmaskable Interrupts ........14-22 MSC8144E Reference Manual, Rev. 3...
Page 16 Fast Back-to-Back Transactions ......15-10 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 17 MIN GNT Configuration Register (MINGNTCR) ....15-33 15.2.3.5 MAX LAT Configuration Register (MAXLATCR) ....15-33 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor xvii...
Page 18 Hits to Multiple ATMU Windows ......16-21 MSC8144E Reference Manual, Rev. 3 xviii...
Page 19 Interrupts........... 16-82 MSC8144E Reference Manual, Rev. 3...
Page 20 (HBDIDLCSR) ..........16-117 16.6.14 Component Tag Command and Status Register (CTCSR) ... . . 16-118 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 21 Error/Port-Write Status Register (EPWISR)......16-147 16.6.41 Logical Retry Error Threshold Configuration Register (LRETCR) ..16-148 16.6.42 Physical Retry Error Threshold Configuration Register (PRETCR) ..16-149 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 22 Inbound Message x Mode Registers (IMxMR)..... . 16-180 16.6.72 Inbound Message x Status Registers (IMxSR) ..... . 16-182 MSC8144E Reference Manual, Rev. 3 xxii Freescale Semiconductor...
Page 23 Channel State ..........17-10 MSC8144E Reference Manual, Rev. 3...
Page 24 SDMA and Bus Error ......... . . 18-9 MSC8144E Reference Manual, Rev. 3...
Page 25 SPI in Multi-Master Operation ........18-43 MSC8144E Reference Manual, Rev. 3...
Page 26 Control Registers..........19-57 MSC8144E Reference Manual, Rev. 3...
Page 27 Idle Input Line Wake-Up (WAKE = 0) ......20-21 MSC8144E Reference Manual, Rev. 3...
Page 28 Software WDT Servicing ........21-15 MSC8144E Reference Manual, Rev. 3...
Page 29 Transaction Monitoring......... . 24-4 MSC8144E Reference Manual, Rev. 3...
Page 30 RD_STATUS Command........25-11 MSC8144E Reference Manual, Rev. 3...
Page 31 Tracing in the MSC8144E........
Page 32 25.3.2.5 Performance Monitor Local Control Bn......25-84 MSC8144E Reference Manual, Rev. 3 xxxii Freescale Semiconductor...
Page 33 Channel Error Interrupt ........26-22 MSC8144E Reference Manual, Rev. 3...
Page 34 F2M_INV: Polynomial Field (F2m) Modular Inversion (0x0E) ..26-34 26.4.1.11.15 MOD_INV: Prime Field (Fp) Modular Inversion (0x0F)... 26-34 MSC8144E Reference Manual, Rev. 3 xxxiv Freescale Semiconductor...
Page 35 AESU Key Registers ......... 26-47 MSC8144E Reference Manual, Rev. 3...
Page 36 KEU IV_2 Register (Fresh) ........26-62 MSC8144E Reference Manual, Rev. 3...
Page 37 PKEU Status Register (PKEUSR) ......26-107 26.5.6.7 PKEU Interrupt Status Register (PKEUISR) ..... . 26-108 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor xxxvii...
Page 38 MDEU ICV Size Register (MDEUICVSR) ..... . . 26-146 26.5.9.9 MDEU End_of_Message Register (MDEUEOMR) ....26-147 MSC8144E Reference Manual, Rev. 3 xxxviii Freescale Semiconductor...
Page 39 RNG Interrupt Mask Register (RNGIMR)......26-184 26.5.12.7 RNG End_of_Message Register (RNGEOMR) ....26-186 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor xxxix...
Page 40 RNG Output FIFO ......... . 26-186 MSC8144E Reference Manual, Rev. 3...
Page 41: About This Book
About This Book The MSC8144E device is based on the StarCore SC3400 DSP core. It addresses the challenges of the media processing networking market. The benefits of the MSC8144E include not only a very high level of performance but also a product design that enables effective software development and integration.
Page 42: Before Using This Manual-Important Note
This manual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8144E. It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on StarCore technology.
Page 43: Notational Conventions And Definitions
For example, BRCGx refers to BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers. On the MSC8144E device, the SC3400 cores are 16-bit DSP processors. The following table shows the SC3400 assembly language data types. For details, see the StarCore SC3400 DSP Core Reference Manual.
Page 44: Conventions For Registers
Chapter 4, Chip-Level Arbitration and Switching System (CLASS). Describes the system switch fabric that allows multi-initiator access to the internal memory and devices and enables high-bandwidth internal data transfers with few bottlenecks. MSC8144E Reference Manual, Rev. 3 xliv Freescale Semiconductor...
Page 45 Chapter 6, Boot Program. Describes the bootloader program that loads and executes source code to initialize the MSC8144E after it completes a reset sequence and programs its registers for the required mode of operation. This chapter covers selection of bootloader modes, normal sequence of events for bootloading a source program, and booting in a multi-processor environment.
Page 46 IEEE® Std. 1149.1™ documentation. The discussion covers the items that the standard requires to be defined and provides additional information specific to the MSC8144E implementation. Also includes debugging resources available in the SC3400 DSP core subsystem, including the OCE modules, and L2 ICache module.
Page 47: Other Msc8144E Documentation
Other MSC8144E Documentation You can find the following documents on the Freescale Semiconductor web site listed on the back cover of this manual. MSC8144E Technical Data Sheet (MSC8144E). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8144E device.
Page 48 MSC8144E Reference Manual, Rev. 3 xlviii Freescale Semiconductor...
Page 49: Overview
In TDM-to-packet applications, for example, data received from the TDM interface is stored in the MSC8144E memory, processed by the SC3400 cores, and transmitted on one of the packet interfaces. In the other direction, packets are received, stored in the MSC8144E memory, processed by the SC3400 cores, and transmitted via the TDM interface.
Page 50: Features
Overview Features Table 1-1 lists the features of the Freescale MSC8144E device. Table 1-1. MSC8144E Features Feature Description Offered with core frequencies of 800 MHz or 1 GHz, supports: • 16 x 16-bit multiply accumulate instructions. Up to 12800/16000 MMACS at 800 MHz/1 GHz within four SC3400 cores.
Page 51 Features Table 1-1. MSC8144E Features (Continued) Feature Description Each high-performance core is binary compatible with the SC140 core used in the MSC81xx DSP family and the SC1400 core used in the MSC711x DSP family and delivers up to 3200/4000 16-bit MMACS using an internal 800 MHz/1 GHz clock at 1 V.
Page 52 Overview Table 1-1. MSC8144E Features (Continued) Feature Description • Three input clocks: – Shared input clock. – Global input clock (PCI PLL). – Differential input clock (SRIO PLL). • Four PLLs: Clocks – System PLL. – Core PLL. – Global PLL.
Page 53 Features Table 1-1. MSC8144E Features (Continued) Feature Description • Up to 200 MHz clock rate (400 MHz data rate). • 16/32-bit DDR SDRAM data bus. • Supported memory includes 64 Mb to 4 Gb DDR1 and DDR2 devices with x8/x16 data ports (no direct x4 support).
Page 54 Overview Table 1-1. MSC8144E Features (Continued) Feature Description The QUICC Engine subsystem handles the Ethernet and ATM interfaces, thus offloading the cores from handling those tasks. It includes the following: • Dual-RISC engine, with one instruction per clock, code execution from internal ROM or multi-port...
Page 55 Features Table 1-1. MSC8144E Features (Continued) Feature Description Universal test and operations PHY interface for ATM (UTOPIA) controller: • UTOPIA level II supports 8/16 bits 25/50 MHz. • UTOPIA target mode. • Cell-level handshake. • Multiple-PHY polling mode. • ATM adaptation layers support AAL0, AAL2, and AAL5 protocols in hardware.
Page 56 Overview Table 1-1. MSC8144E Features (Continued) Feature Description • Two outbound message queues. • Two inbound message queues. RapidIO • One outbound doorbell queue. Messaging Unit • One inbound doorbell queue. • One inbound port-write queue. Consolidates all chip maskable interrupt and non-maskable interrupt sources and routes them to Global Interrupt INT_OUT, NMI_OUT, and the cores.
Page 57: Block Diagram
M3 power: 1.2 V. • I/O power: 1.8 V/2.5 V/3.3 V. Block Diagram Figure 1-2 shows the MSC8144E block diagram. Arrows are in the direction from initiator to target. DDR Interface 16/32-bit at 400 MHz data rate I/O-Interrupt 10 Mbytes...
Page 58: Architecture
The MSC8144E architecture is carefully optimized to achieve the maximum channel density for a given device area, power, and cost. Also, the MSC8144E is a derivative of the same system internal platform Freescale uses to implement new DSPs. Therefore, Freescale can swiftly spin off DSP devices from the same platform and provide the customer with familiar modules and programming models.
Page 59: Starcore Sc3400 Dsp Core
40-bit adder/subtractor. Each ALU performs one MAC operation per clock cycle, so a single core running at 800 MHz/1 GHz can perform up to 3.2/4 GMACS. Each AAU in the AGU MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 60: L1 Instruction Cache
This option, referred to as prefetch, takes advantage of the spatial locality of the code. When a new fetch is required and all the ways of the MSC8144E Reference Manual, Rev. 3 1-12...
Page 61: L1 Data Cache
This instruction is used when the data in the cache is no longer valid—for example, when the I/O device brings new data into the MSC8144E memory. Flush memory zone. The DCache invalidates and writes to the MSC8144E memory all lines belonging to the specified zone and a specific task.
Page 62: Memory Management Unit (Mmu)
Relocatable code is not immune to addressing problems. Global variables can be addressed relative to the code. However, in a multi-core device such as MSC8144E in which all the cores may share the same code, these global variables should be addressed differently depending on the core.
Page 63: Debug And Profiling Unit (Dpu)
A selection of trace writing policies implements protocols such as continuous double-buffered DMA uploads, continuous writes for failure point history, and more. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 1-15...
Page 64: Chip-Level Arbitration And Switching System (Class)
User data written by the core software to a specified DPU memory mapped address. Chip-Level Arbitration and Switching System (CLASS) The CLASS is the central interconnect system for the MSC8144E device. The CLASS is a non-blocking, full fabric crossbar switch, that gives any initiator access to any target in parallel with another initiator-target couple.
Page 65: Memory System
The M3 memory supports partial, full, and burst accesses. The M3 memory includes hidden refresh with a low probability of conflict with core accesses, and it supports burstable accesses. The M3 memory is fully ECC protected. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 1-17...
Page 66: L2 Instruction Cache
Clocks The MSC8144E device has three input clocks: A shared input clock for the system PLL, core PLL, and global PLL. — The core PLL can get an input clock either from the “shared input clock” or from the output of the system PLL (cascaded).
Page 67: Ddr Controller (Ddrc)
When the MSC8144E device works with channel data stored in the DDR SDRAM, the DMA controller can swap the data to and from the M2 memory, thus enabling the L1 DCache to fetch from M2 memory instead of accessing the DDR SDRAM memory directly.
Page 68: Dma Controller
TDMs support either 0.5 ms (4 frames) or 1 ms (8 frames) latency. The buffers of one TDM interface are the same size and are filled/emptied at the same rate. A-law/u-law buffers are filled MSC8144E Reference Manual, Rev. 3 1-20...
Page 69: Quicc Engine Subsystem
1.11 QUICC Engine Subsystem The MSC8144E QUICC Engine module is a versatile communications engine based on a subset of the Freescale QUICC Engine technology that integrates several communications peripheral controllers. Note: See the QUICC Engine Block Reference Manual with Protocol Interworking (QEIWRM) for functional, register, and programming details.
Page 70: Ethernet Controllers
The rate of these clocks can be up to one-half of the QUICC Engine module clock frequency. However, the ability of an interface to support a sustained bit stream depends on the protocol settings and other factors. Figure 1-5 shows the MSC8144E QUICC Engine module block diagram. CLASS 32-Bit...
Page 71 (RxBD) from FIFO. If RxBD is not being used by the software (RxBD[E] is set), the controller starts transferring the incoming frame. RxBD[F] is set for the first RxBD used for any particular receive frame. When the buffer is filled, the Ethernet MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 1-23...
Page 72: Atm Controller
1.12 The PCI interface connects the MSC8144E device to a 33 or 66 MHz, 3.3 V PCI bus to which the I/O components are connected. The PCI interface complies with the PCI Local Bus Specification, Revision 2.2.
Page 73: Serial Rapidio Subsystem
MSC8144E memory, it uses buffer descriptors (BDs) that are messaged from the DSP core to the host. The host may put all the data buffers into its memory and have the MSC8144E access the data.
Page 74: Rapidio Messaging Unit (Rmu) Operation
The doorbell receiver functions in much the same way except for filtering according to a selected field in the header only. The message transmitter performs the following steps: MSC8144E Reference Manual, Rev. 3 1-26 Freescale Semiconductor...
Page 75: Global Interrupt Controller (Gic)
During transmission, the UART generates an interrupt request when its data register can be written with new character. When accepting an interrupt request, an SC3400 core or external host should read the UART status register to identify the interrupt source and service it accordingly. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 1-27...
Page 76: Timers
In addition, each SC3400 subsystem includes two general purpose 32-bit timers. The MSC8144E device also includes 5 software watchdog timers. Each of the software watchdog timers can be used by any of the cores within MSC8144E as well as by an external host. 1.17 Hardware Semaphores There are eight coded hardware semaphores.
Page 77: Boot Options
1.21 Boot Options The boot program in the internal boot ROM initializes the MSC8144E after it completes a reset sequence. The MSC8144E device can boot from an external host through the serial RapidIO or PCI interfaces or download a user boot program through the I C or Ethernet ports.
Page 78: Application Software
Host Platform Support. Microsoft Windows and Solaris. Development Board. The application development system (ADS). Kit for MSC8144E. A complete system for developing and debugging real-time hardware and software. The kit includes the MSC8144E device with a companion memory connected to a RapidIO switch and connects to a host processor, JTAG debug interface, serial and Ethernet interface, and software device drivers.
Page 79 G.168 2004 (128 ms, windowed) Noise reduction Acoustic level control Acoustic EC (roadmap) Telephony support DTMF detection Universal tone generation Special tone event detect VAD/CNG RTP packetization Security Video MPEG4 H.263 H.264 H.324MDSP (roadmap) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 1-31...
Page 80: Example Applications
The applications covered in this section are as follows: Application 1. Generic System Block Diagram. Application 2. Legacy Farm Example using UTOPIA and TDM. Application 3. System solution. Application 4. SerDes connectivity. MSC8144E Reference Manual, Rev. 3 1-32 Freescale Semiconductor...
Page 81: Application 1
I/O protocol support. A generic system block diagram is shown in Figure 1-7. For completeness, DDR SDRAMs are shown attached to the MSC8144E devices, but for most applications the onboard memory is all that is required. This is true of the examples that follow.
Page 82: Application 2
In this system, the UTOPIA level 2 provides the packet (cell) based interface via either AAL2 or AAL5. To provide the PCM side, TDM is used. The UL2 interface on MSC8144E provides parsing into the IP packet contained in the AAL5 cps. For AAL2, it can support multiple AAL2 cps packets per cell.
Page 83: Application 3
PowerQUICC device. TDM is used for the PCM side. For such solutions, no time-slot assigner is required because the MSC8144E devices can interface with an H.110-like bus. MSC8144E Reference Manual, Rev. 3...
Page 84: Application 4
EEPROM Figure 1-10. SerDes Connectivity This example considers the SerDes interface. For MSC8144E, the interface can use either a gigabit Ethernet (SGMII) or Serial RapidIO. Thus, MSC8144E is AMC/advanced TCA ready. In this example, an H.110 TDM bus is used. For AMC, this bus would be on the extended connector with the SerDes in the fabric area.
Page 85: Application 5
An application blade server that executes the radio network layer (RNL) to process RNC traffic using the MSC8144E is shown in is shown in Figure 1-11. This example is a farm of MSC8144E devices with external memory. The blade example shows both SerDes type interfaces on the card;...
Page 86 Overview MSC8144E Reference Manual, Rev. 3 1-38 Freescale Semiconductor...
Page 87: Sc3400 Core Overview
Dynamic interlocking for friendlier programming, more efficient compiler support, and reduced code size. User and supervisor privilege levels supporting a protected software model. Precise memory access exceptions enables good RTOS support and soft error corrections. Branch target buffer (BTB) accelerates change-of-flow operations. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 88: Architecture
Register File Module Register File 2 AAUs 4 ALUs Controller DALU PSEQ Instruction Bus JTAG Port Resource Stall Unit (RSU) SC3400 Core Figure 2-1. Block Diagram of the SC3400 Core in the MSC8144E MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 89: Data Arithmetic Logic Unit (Data Alu)
2.1.1 Data Arithmetic Logic Unit (Data ALU) The Data ALU performs arithmetic and logical operations on data operands in the MSC8144E. The data registers can be read or written to memory over the Xa data bus and the Xb data bus as 8-bit, 16-bit, or 32-bit operands.
Page 90: Data Registers
The AGU operates in parallel with other chip resources to minimize address generation overhead. The AGU also generates change-of-flow program addresses and manages the stack pointer (SP). The major components of the AGU are as follows: MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 91 Arithmetic Unit (AAU) B3/R1 B4/R1 MCTL B5/R1 B6/R1 B7/R1 NSP, ESP Mask Program Counter (PC) Address Unit (BMU) Memory Data Bus 1 (Xa_DATA) Memory Data Bus 2 (Xb_DATA) Figure 2-2. AGU Block Diagram MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 92: Stack Pointer Registers
Stack instructions use the ESP when the MSC8144E is in the Exception mode of operation, which it enters when exceptions occur. The NSP is used in Normal mode, while not servicing an exception.
Page 93: Program Sequencer Unit (Pseq)
SC1000-family core legacy code. 2.1.5 On-Chip Emulator (OCE) The OCE module allows nonintrusive interaction with the MSC8144E and its peripherals so that you can examine registers, memory, or on-chip peripherals, define various breakpoints, and read the trace-FIFO. These interactions facilitate hardware and software development on the MSC8144E processor.
Page 94: Programming Model
The address register modification is performed by either of the two AAUs. Stack Pointer Registers (NSP, ESP). The MSC8144E has two stack pointer registers: the Normal Stack Pointer (NSP) and the Exception Stack Pointer (ESP). These 32-bit registers are used implicitly in all PUSH and POP instructions.
Page 95 Modifier Control Register (MCTL). The 32-bit read/write register to program the address mode (AM) for each of the eight address registers (R[0–7]). The addressing mode of the upper address register file (R[8–15]) cannot be programmed and functions in linear mode only. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 96 D13 D13.e D13.h D13.I D14 D14.e D14.h D14.I D15 D15.e D15.h D15.I Program Status Mode and Exception Counter Register Status Register Start Address Loop Counter Registers Registers Figure 2-3. SC3400 Programming Model MSC8144E Reference Manual, Rev. 3 2-10 Freescale Semiconductor...
Page 97: Data Arithmetic Logic Programming Model
When a byte operand is to be written to a data register, the register’s first eight bit portion of the LSP (Dx.1[7–0]) is written with the byte operand, and the remaining bits are either zero-extended or sign-extended from the LSP lower byte. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 2-11...
Page 98: Program Control Unit Programming Model
All of the specified bits are read-only and cannot be changed by the user except as indicated above by the input signal or HCRW bit names. The device design selects big-endian mode for core operation, as indicated by BEM = 1. GP4 equals the inversion of the HRCW bit 13. MSC8144E Reference Manual, Rev. 3 2-12 Freescale Semiconductor...
Page 99: Instruction Set Overview
Two word absolute values Add long with carry ADD.W Add 16-Bit Value ADD2 Add two words ADDNC.W Add without changing the carry bit in the SR Add and round Arithmetic shift left by one bit MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 2-13...
Page 100 Saturate two signed words to fit in unsigned bytes SAT2.W Saturate two 20-bit words to fit 16-bit words Subtract long with carry Subtract and round SOD2ffcc Sum Or Difference of Two 16-Bit Values, function & cross MSC8144E Reference Manual, Rev. 3 2-14 Freescale Semiconductor...
Page 101 Multiply signed by unsigned and accumulate with data register right shifted by word size IMAC Multiply-accumulate integers IMACLHUU Multiply-accumulate unsigned integers; first source from low portion, second from high portion IMACSU2 Two multiply-accumulate of signed by unsigned integer bytes MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 2-15...
Page 102 Swap the bytes in each word (for BE8/LE8 support) SXT.B Sign extend byte SXT.L Sign extend long SXT.W Sign extend word ZXT.B Zero extend byte ZXT.L Zero extend long ZXT.W Zero extend word MSC8144E Reference Manual, Rev. 3 2-16 Freescale Semiconductor...
Page 103 Decrement and set T if zero DECGEA Decrement and set T if equal or greater than zero INCA Increment register LSRA Logical shift right (32-bit) SUBA Subtract (affected by the modifier mode) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 2-17...
Page 104 Move four fractional words to memory with scaling and limiting enabled MOVES.F Move fractional word to memory with scaling and limiting enabled MOVES.L Move long to memory with scaling and limiting enabled MSC8144E Reference Manual, Rev. 3 2-18 Freescale Semiconductor...
Page 105 Logical AND on a 16-bit operand BMCHG Bit-mask change a 16-bit operand BMCHG.W Bit-mask change a 16-bit operand in memory BMCLR Bit-mask clear a 16-bit operand BMCLR.W Bit-mask clear a 16-bit operand in memory MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 2-19...
Page 106 Jump if false Jump if false (delayed) Jump JMPD Jump (delayed) Jump to subroutine JSRD Jump to subroutine (delayed) Jump if true Jump if true (delayed) Return from exception RTED Return from exception (delayed) MSC8144E Reference Manual, Rev. 3 2-20 Freescale Semiconductor...
Page 107 Trigger a precise illegal instruction exception MARK Push the PC into the trace buffer STOP Stop processing (lowest power stand-by) SYNCIO Synchronize I/O SYNCM Synchronize Memory WAIT Wait for interrupt (low power stand-by) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 2-21...
Page 108: Additional Programming Considerations
Execute current execution set or subgroup if the T bit is set No operation 2.4 Additional Programming Considerations All code sections must end with an unconditional cof instruction. This can be either a cof or a delayed cof instruction. MSC8144E Reference Manual, Rev. 3 2-22 Freescale Semiconductor...
Page 109: External Signals
External Signals The MSC8144E external signals are organized into functional groups. Table 3-1 lists the functional groups and references the table that gives a detailed listing of signals within each group. Table 3-1. MSC8144E Functional Signal Groupings Functional Group Detailed Description...
Page 110 Ethernet 2 SMII/RMII/ SMII/RMII/ SMII/RMII/ SMII/RMII/ SGMII SMII/RMII/ SMII/RMII/ SMII/RMII/ SGMII SGMII SGMII SGMII RGMII/ RGMII/ SGMII SGMII SGMII Clocks, JTAG, C, Reset, DDR, RapidIO, and Supported in all modes UART Total GPIO MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 111 GPIO configuration registers (see Chapter 23, GPIO for details) that permit sharing of signals among the GPIO ports, maskable interrupt inputs, timers, UART, I C, and some TDM interfaces. Figure 3-1 shows MSC8144E external signals organized by function. MSC8144E Reference Manual, Rev. 3...
Page 112 UTP_RD8 multiplexed Multiplexed I/O See Table 3-2 ↔ ↔ signals by I/O mode. RC13 UTP_RD9 for the ↔ ↔ RC14 UTP_TXPRTY Multiplexed I/O. ↔ ↔ RC15 UTP_TXSOC ↔ Figure 3-1. MSC8144E External Signals MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 113: Power Signals
M3 Internal Logic (1.2 V) DDM3 A dedicated well-regulated power source for the M3 internal logic. Provide an extremely low impedance path to the power rail. The external decoupling capacitors recommendations are listed in the MSC8144E Technical Data Sheet. M3 I/O Power (2.5 V) DDM3IO A dedicated well-regulated power source for the M3 I/O signals.
Page 114: Clock Signals
3.2 Clock Signals Table 3-4. Clock Signals Signal Name Type Signal Description CLKIN Input Clock In Primary clock input to the MSC8144E PLLs. CLKOUT Output Clock Out The bus clock output. PCI_CLK_IN Input PCI Input Clock Input clock for the PCI module.
Page 115: Reset And Configuration Signals
Soft Reset Output When asserted as an input, this signal causes the MSC8144E to enter the soft reset state, about all current internal transactions, configure most registers with their default values, and cause the cores to enter their reset state. The signal does not affect I/O signal functionality or direction or memory controller operations.
Page 116 TDM1 Serial Transmitter Data Output The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1. For configuration details, see Chapter 20, TDM Interface. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 117 TDM3 Receive Frame Sync Output The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3. For configuration details, see Chapter 20, TDM Interface. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 118 PORESET to set part of the bits of the Reset Configuration Word Registers. The required signal levels must be maintained as long as HRESET is asserted. All other signal drivers connected to these inputs must be tri-stated while HRESET is asserted. MSC8144E Reference Manual, Rev. 3 3-10 Freescale Semiconductor...
Page 119: Memory Controller
MDQ[31–0] Input/ Data Bus Output The MSC8144E device drives the bus during write cycles and the external memory drives the bus during read cycles. MDM[3–0] Output DDR SDRAM Data Output Mask Masks unwanted data bytes transferred during a burst write. These signals are used to support sub-burst-size transactions (such as single-byte writes) on SDRAM in which all transactions occur in multi-byte bursts.
Page 120: Serial Rapidio Signals
Serial data input for a 4x link. Each signal is part of a differential pair. GE2_SGMII_RX Input Ethernet 2 SGMII Receive Data Part of the Ethernet signals. For details, see Chapter 20, Ethernet Controller. MSC8144E Reference Manual, Rev. 3 3-12 Freescale Semiconductor...
Page 121 SGMII operation, this provides the input clock. Note: For proper definition of serial RapidIO modes (1x/4x) and SGMII, configure the interfaces using the Reset Configuration Word settings. For details, see Chapter 5, Reset. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-13...
Page 122: Pci Signals
Output Ethernet 1 Transmit Data 2 1,2,6 For details, see Chapter 19, Ethernet Controller. UTP_TD4 Output ATM UTOPIA Transmit Data 4 0,4,5,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-14 Freescale Semiconductor...
Page 123 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_TADDR1 Input/ ATM UTOPIA Transmit Address 1 0,1,3,4,5,6, Output For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-15...
Page 124 PCI Address/Data Line 21 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_RPRTY Input ATM UTOPIA Receive Parity 0,1,3,4,5,6, For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-16 Freescale Semiconductor...
Page 125 Input/ TDM6 Receive Clock 0,1,2,5,6 Output The receive clock signal for TDM 6. Selected through GPIO configuration. For details, see Chapter 23, GPIO. For TDM configuration details, see Chapter 20, TDM Interface. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-17...
Page 126 PCI Address/Data Line 15 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_RD11 Input ATM UTOPIA Receive Data 11 0,1,3,4,5,6, For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-18 Freescale Semiconductor...
Page 127 TDM4TSYN Input/ TDM4 Transmit Sync Output Transmit sync signal for TDM 4. Selected through GPIO configuration. For 0,1,2,5,6 details, see Chapter 23, GPIO. For TDM configuration details, see Chapter 20, TDM Interface. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-19...
Page 128 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_RADDR0 Input/ ATM UTOPIA Receive Address 0 0,1,3,4,5,6, Output For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-20 Freescale Semiconductor...
Page 129 The receive sync signal for TDM 7. As an input, this can be the DATA_B data signal for TDM 7. For configuration details, see Chapter 20, TDM Interface. GE2_TD2 Output Ethernet 2 Transmit Data 2 For details, see Chapter 19, Ethernet Controller. UTP_TER Output Transmit Error MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-21...
Page 130 GE1_TX_ER Output Ethernet 1 Transmit Error 1,2,6 For details, see Chapter 19, Ethernet Controller. UTP_TD7 Output ATM UTOPIA Transmit Data 7 0,4,5,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-22 Freescale Semiconductor...
Page 131 GPIO configuration. For details, see Chapter 23, GPIO. For timer functional details, see Chapter 22, Timers. UTP_IR Input UTOPIA IR 0,1,3,5,6,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-23...
Page 132 Input Ethernet 1 Receive Data 2 1,2,6 For details, see Chapter 19, Ethernet Controller. UTP_RD4 Input ATM UTOPIA Receive Data 4 0,4,5,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-24 Freescale Semiconductor...
Page 133 One of the sixteen external lines that can request a service routine via the internal interrupt controller. Configured as part of the GPIO port. For details, see Chapter 23, GPIO. For functional details, see Chapter 13, Interrupt Handling. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-25...
Page 134 PCI System Error Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_TD0 Output ATM UTOPIA Transmit Data 0 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. 0,1,4,5,6,7 MSC8144E Reference Manual, Rev. 3 3-26 Freescale Semiconductor...
Page 135: Ethernet Signals
TDM 7. For configuration details, see Chapter 20, TDM Interface. PCI_AD1 Input/ PCI Address/Data Line 1 2,3,4 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_STA Output Transmit Start-of-Packet MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-27...
Page 136 Input Ethernet 2 Receive Clock 0,1,2,3,5,6, For details, see Chapter 19, Ethernet Controller. PCI_AD29 Input/ PCI Address/Data Line 29 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-28 Freescale Semiconductor...
Page 137 PCI Frame Sync Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_RD4 Input ATM UTOPIA Receive Data 4 0,4,5,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-29...
Page 138 Ethernet 1 Receive Data Valid 1,2,6 Part of the Ethernet signals. For details, see Chapter 19, Ethernet Controller. UTP_RD7 Input ATM UTOPIA Receive Data 7 0,3,4,5,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. MSC8144E Reference Manual, Rev. 3 3-30 Freescale Semiconductor...
Page 139 Inverted serial data input for a 4x link. Each signal is part of a differential pair. GE2_SGMII_RX Input Ethernet 2 SGMII Receive Data Inverted Part of the Ethernet signals. For details, see Chapter 20, Ethernet Controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-31...
Page 140: Atm Utopia Signals
ATM UTOPIA Transmit Data 12 0,1,3,4,5,6, For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. PCI_CBE2 Input/ PCI Byte 2 Enable Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-32 Freescale Semiconductor...
Page 141 PCI Address/Data Line 29 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. GE1_TD2 Output Ethernet 1 Transmit Data 2 1,2,6 For details, see Chapter 19, Ethernet Controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-33...
Page 142 ATM UTOPIA Receive Data 11 0,1,3,4,5,6, For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. PCI_AD15 Input/ PCI Address/Data Line 15 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-34 Freescale Semiconductor...
Page 143 PCI Byte 3 Enable Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. GE1_RD1 Input Ethernet 1 Receive Data 1 1,2,6 For details, see Chapter 19, Ethernet Controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-35...
Page 144 ATM UTOPIA Receive Address 3 0,1,3,4,5,6, Output For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. PCI_AD10 Input/ PCI Address/Data Line 10 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-36 Freescale Semiconductor...
Page 145 0,1,3,4,5,6, PDRPA Output For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. Input/ PCI Address/Data Line 12 PCI_AD12 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-37...
Page 146 Chapter 21, Timers. GPIO20 Input/ General-Purpose Input Output 20 0,1,2,3,5,6 Output One of 32 GPIOs. For details, see Chapter 22, GPIO. PCI_PAR Input/ PCI Parity Output For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-38 Freescale Semiconductor...
Page 147 GE2_TD3 Output Ethernet 2 Transmit Data 3. UTP_RER Input Receive Error TDM7TCLK Input TDM7 Transmit Clock Transmit Clock for TDM 7. PCI_IDSL Input PCI IDSL. 2,3,4 GE2_TCK Output Ethernet 2 Transmit Clock MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-39...
Page 148 The receive sync signal for TDM 7. As an input, this can be the DATA_B data signal for TDM 7. PCI_AD2 Input/ PCI Address/Data Line 2 2,3,4 Output Part of the PCI address/data bus. GE2_TD2 Output Ethernet 2 Transmit Data 2 MSC8144E Reference Manual, Rev. 3 3-40 Freescale Semiconductor...
Page 149: Serial Peripheral Interface (Spi) Signal Summary
Gated clock, active only during data transfers. Four combinations of SPICLK phase and polarity can be configured. When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-41...
Page 150: Gpio/Maskable Interrupt Signal Summary
General-Purpose Input Output 27 All modes Output One of 32 GPIOs. For details, see Chapter 23, GPIO. Input/ C-Bus Data Line All modes Output This is the data line for the I C bus. MSC8144E Reference Manual, Rev. 3 3-42 Freescale Semiconductor...
Page 151 Configured as input to the counter or output from the counter. Selected through the GPIO configuration. For details, see Chapter 23, GPIO. For timer functional details, see Chapter 22, Timers. PCI_PAR Input/ PCI Parity Output For details, see Chapter 15, PCI. UTP_REOP Input Receive End-of-Packet MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-43...
Page 152 One of sixteen external lines that can request a service routine via the internal interrupt controller. For details, see Chapter 13, Interrupt Handling. UTXD Input/ UART Transmit Data All modes Output For details, see Chapter 21, UART. MSC8144E Reference Manual, Rev. 3 3-44 Freescale Semiconductor...
Page 153 The receive sync signal for TDM 5. As an input, this can be the DATA_B data signal for TDM 5. For configuration details, see Chapter 20, TDM Interface. PCI_AD15 Input/ PCI Address/Data Line 15 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-45...
Page 154 The receive sync signal for TDM 6. For configuration details, see Chapter 20, TDM Interface. PCI_AD21 Input/ Output PCI Address/Data Line 21 Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-46 Freescale Semiconductor...
Page 155 All modes Output One of 32 GPIOs. For details, see Chapter 23, GPIO. GPIO0 Input/ General-Purpose Input Output 0 All modes Output One of 32 GPIOs. For details, see Chapter 23, GPIO. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-47...
Page 156: Timer Signals
One of 32 GPIOs. For details, see Chapter 23, GPIO. UTP_IR Input UTOPIA IR 0,1,3,5,6,7 For details, see Chapter 18, Asynchronous Transfer Mode (ATM) Controller. PCI_CBE3 Input/ PCI Byte Enable 3 Output For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-48 Freescale Semiconductor...
Page 157: Uart Signals
One of the sixteen external lines that can request a service routine, via the internal interrupt controller. Selected through the GPIO configuration. For configuration details, see Chapter 23, GPIO. For functional details, see Chapter 13, Interrupt Handling. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-49...
Page 158: I 2 C Signals
Transmit frame sync for TDM 7. See Chapter 20, TDM Interface. PCI_AD4 Input/ PCI Address/Data Line 4 2,3,4 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. UTP_RMOD Input Receive Word Modulo MSC8144E Reference Manual, Rev. 3 3-50 Freescale Semiconductor...
Page 159 Transmit clock for TDM 6. For configuration details, see Chapter 20, TDM Interface. PCI_AD22 Input/ PCI Address/Data Line 22 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-51...
Page 160 Selected through the GPIO port; see Chapter 23, GPIO. For functional details, see Chapter 13, Interrupt Handling. PCI_AD19 Input/ PCI Address/Data Line 19 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-52 Freescale Semiconductor...
Page 161 General-Purpose Input Output 9 0,1,2,5,6 Output One of 32 GPIOs. For details, see Chapter 23, GPIO. PCI_AD14 Input/ PCI Address/Data Line 14 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-53...
Page 162 The receive clock signal for TDM 4. As an output, this can be the DATA_C data signal for TDM 4. For configuration details, see Chapter 20, TDM Interface. PCI_AD7 Input/ PCI Address/Data Line 7 Output Part of the PCI address/data bus. For details, see Chapter 15, PCI. MSC8144E Reference Manual, Rev. 3 3-54 Freescale Semiconductor...
Page 163 Used to load part of the Reset Configuration Word during Reset. TDM2TCLK Input TDM 2 Transmit Clock All modes Transmit clock for TDM 2. For configuration details, see Chapter 20, TDM Interface. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-55...
Page 164 TDM1 Receive Clock All modes Output The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For configuration details, see Chapter 20, TDM Interface. MSC8144E Reference Manual, Rev. 3 3-56 Freescale Semiconductor...
Page 165 TDM 0. For configuration details, see Chapter 20, TDM Interface. RCW_SRC0 Input Reset Configuration Word Source 0 Reset Along with the RCW_SRC[1–2], this signal is sampled at the deassertion of PORESET to identify the source of the reset configuration word. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-57...
Page 166: Other Interrupt Signals
3.16 OCE Event and JTAG Test Access Port Signals The MSC8144E uses two sets of debugging signals for the two types of internal debugging modules: OCE and the JTAG TAP controller. Each internal SC3400 core has an OCE module, but they are all accessed externally by the same two signals .
Page 167 OCE Event and JTAG Test Access Port Signals MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 3-59...
Page 168 External Signals MSC8144E Reference Manual, Rev. 3 3-60 Freescale Semiconductor...
Page 169: Chip-Level Arbitration And Switching System (Class)
The Chip Level Arbitration and Switching System (CLASS) is the central internal interconnect system for the MSC8144E device. The CLASS is a non-blocking, full-fabric crossbar switch that allows any initiator to access any target in parallel with another initiator-target couple. The CLASS uses a fully pipelined low latency design.
Page 170 Figure 4-1. CLASS Initiators and Targets in the MSC8144E Device The CLASS system uses three CLASS modules (CLASS0, CLASS1, and CLASS2) in the MSC8144E device to implement the required interface paths. Each CLASS module provides all the CLASS features. Controller...
Page 171: Class Features
— The CLASS identifies illegal addresses; addresses that do not belong to any of the address windows or fall inside the negative windows. — The CLASS stores the illegal address, reports the error, and generates an interrupt. Debug and profiling unit (CDPU) support. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 172: Functional Description
For more details about normalizer module see Section 4.2.3. The MSC8144E device CLASS modules support different bus widths, numbers of initiator devices, and number of target devices. Table 4-1 lists the characteristics of the three CLASS modules.
Page 173: Multiplexer And Arbiter Module
(no priority upgrade ability by the initiator and auto priority upgrade in the expander module is disabled). When the Masking Priority is enabled, the arbiter dedicates slots for lower priority initiator in which the higher priority initiators are masked. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 174: Weighted Arbitration
CnPAVRx[AUV] (see Section 4.7.3, CLASS Priority Auto Upgrade Value Registers (CnPAVRx)). The upgrade level and timing depend on the current priority value assigned, as follows: MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 175: Class Multiplexer
An address which does not belong to any of the address space windows of the enabled address decoders. An address which falls within any of the address space windows of the enabled error address decoders. When an illegal address is identified by the CLASS, the following events occur. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 176 The error interrupt is logically ORed with internal error interrupts. The internal error interrupts are associated with each initiator. Thus, the CLASS error interrupt is asserted when at least one internal interrupt is asserted. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 177: Class Debug Profiling Unit
(CPRCR) starts counting the clock cycles. Read the CPISR[OVE] bit to verify that the measurement is complete and that the profiling counter values are valid. If the CPISR[OVE] is clear, read the profiling counters CPRCR and CPGCR and analyze the results. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 178: Watch Point Unit
— — — Initiator Priority — 00001 Number of Number of Number of Initiator Initiator Initiator Initiator Auto- Auto-Upgrade requests requests requests Upgrade with with with Priority 1 Priority 2 Priority 3 MSC8144E Reference Manual, Rev. 3 4-10 Freescale Semiconductor...
Page 179 Bandwidth Read Data Write Data Target Stall — 00000 Target T Target T — — Write After Write After Read Read Stall Watch Point — 00000 Watch — — — Point Event MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-11...
Page 180: Debug And Profiling Events
The CLASS configuration registers are reset as described in the table for each register in Section 4.7, Programming Model. 4.5.2 Hard Reset This reset brings all states machines to idle state and sets all CLASS registers to the reset values. MSC8144E Reference Manual, Rev. 3 4-12 Freescale Semiconductor...
Page 181: Limitations
This situation can be prevented by using the auto priority upgrade supported by the expander module and/or by the multiplexer and arbiter module priority mask mechanism. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-13...
Page 182: Programming Model
CLASS1 End Address Decoder x (see page 4-47) CLASS1 Attributes Decoder x (see page 4-48) Note: The base addresses for addressing registers are as follows: CLASS0 = 0xFFF18000 CLASS1 = 0xFFF19000 CLASS2 = 0xFFF1A000 MSC8144E Reference Manual, Rev. 3 4-14 Freescale Semiconductor...
Page 183: Class Mbus Target Configuration Registers (Cnmtcrx)
(fast) while maintaining coherency for the last data in a block (real). 4-3 lists the CnMTCRx bit field descriptions. Note: The MSC8144E boot program configures these registers to maintain coherency. Reconfiguration by the user is not recommended. Table 4-3. CnMTCRx Bit Descriptions...
Page 184 (for example, 3 bytes or 17 bytes). When the target requires a burst request to be aligned to the datum set the DA bit. — Reserved. Write to 0 for future compatibility. MSC8144E Reference Manual, Rev. 3 4-16 Freescale Semiconductor...
Page 185: Class Priority Mapping Registers (Cnpmrx)
This register also enables/disables the priority derivation feature. Note: You cannot write to this register while there are open CLASS transactions. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-17...
Page 186 Reserved. Write to 0 for future compatibility. 3–2 Priority Mapping 0 Priority 0 1–0 Holds the priority value assigned to Priority 1 transactions that arrive with a value of 0. Priority 2 Priority 3 MSC8144E Reference Manual, Rev. 3 4-18 Freescale Semiconductor...
Page 187: Class Priority Auto Upgrade Value Registers (Cnpavrx)
• Priority 1: Bits 15–1 are loaded into bit 14–0 of the counter and a 0 into bit 15. • Priority 2: Bits 15–2 are loaded into bits 13–0 of the counter and 0 into bits 15 and 14. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 188: Class Priority Auto Upgrade Control Registers (Cnpacrx)
— Reserved. Write to 0 for future compatibility. 31–1 Auto-Upgrade Enable Auto-upgrade mechanism disabled. Enables/disables the auto-upgrade Auto-upgrade mechanism enabled. mechanism. Note: This bit can only be cleared by a hardware reset. MSC8144E Reference Manual, Rev. 3 4-20 Freescale Semiconductor...
Page 189: Class 1 Error Address Registers (C1Earx)
— C1EAR2 = Address generated by one of the 4 cores on the instruction bus or the L2 ICache. — C1EAR3 = Address generated by a QUICC Engine peripheral. — C1EAR4 = Address generated by the RapidIO controller, TDM, or PCI inbound. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-21...
Page 190: Class 1 Error Extended Address Registers (C1Eearx)
Reserved. Write to 0 for future compatibility. Atomic Access Not atomic access. This field indicates whether the transaction that caused the Atomic access. error was an atomic access. — Reserved. Write to 0 for future compatibility. 11–9 MSC8144E Reference Manual, Rev. 3 4-22 Freescale Semiconductor...
Page 191 0x15 PCI controller 0x16– 0x17 reserved 0x18 DMA port 1 0x19– 0x1F reserved ERR_ADD Error Address 3–0 This field stores the 4 msbs of the address of the internal transaction that caused the error. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-23...
Page 192: Class Initiator Profiling Configuration Registers (Cnipcrx)
00101 Initiator priority non-upgrade. 00110 Initiator supervisor. 00111 Initiator bandwidth. 01000– 01111 reserved 10000 Target 0 bandwidth. 10001 Target 1 bandwidth. 10101 Target 5 bandwidth. 10110– 11111 reserved MSC8144E Reference Manual, Rev. 3 4-24 Freescale Semiconductor...
Page 193: Class Initiator Watch Point Control Registers (Cniwpcrx)
Reserved. Write to 0 for future compatibility. 31–1 WPEN Watch Point Enable The watch point is disabled. Enables/disables the auto-upgrade The watch point is enabled. mechanism. Note: This bit can only be cleared by a hardware reset. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-25...
Page 194: Class Arbitration Weight Registers (Cnawrx)
— Reserved. Write to 0 for future compatibility. 31–4 WEIGHT Weight 3–0 Contains the arbitration weight assigned to the associated initiator. Note: This register can only be cleared by a hardware reset. MSC8144E Reference Manual, Rev. 3 4-26 Freescale Semiconductor...
Page 195: Class Irq Status Register (Cnisr)
• CLASS0 supports six bits. • CLASS1 supports five bits. • CLASS2 supports three bits. The remaining bits are reserved. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-27...
Page 196: Class Irq Enable Register (Cnier)
• CLASS0 supports six bits. • CLASS1 supports five bits. • CLASS2 supports three bits. The remaining bits are reserved. MSC8144E Reference Manual, Rev. 3 4-28 Freescale Semiconductor...
Page 197: Class Target Profiling Configuration Register (Cntpcr)
Reserved. Write to 0 for future compatibility. 31–13 Target Type Arbiter. Selects the module used for target Normalizer. profiling. Used with PMM. See PMM settings. — Reserved. Write to 0 for future compatibility. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-29...
Page 198 00 No profiling measurement. selected target. 01 Arbitration winner priority measurement. 10 Collisions measurement. 11 reserved. If TT = 1: 00 No profiling measurement. 01 Transaction splitting measurement. 10 Bandwidth measurement. 11 Stall measurement. MSC8144E Reference Manual, Rev. 3 4-30 Freescale Semiconductor...
Page 199: Class Profiling Control Register (Cnpcr)
Time-out function disabled. Enables/disables the time-out mechanism. Time-out function enabled. — Reserved. Write to 0 for future compatibility. 3–1 Profiling Enable Profiling unit disabled. Enables/disables the debug profiling unit Profiling unit enabled. operation. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-31...
Page 200: Class Watch Point Control Registers (Cnwpcr)
Enables/disables the atomic result type Atomic result type compare with CnWPACR comparison. enabled. ATAE Atomic Access Compare Enable Atomic access type compare disabled. Enables/disables the atomic access type Atomic access type compare with CnWPACR comparison. enabled. MSC8144E Reference Manual, Rev. 3 4-32 Freescale Semiconductor...
Page 201 Enables/disables comparison of the Address compare with CnWPACR enabled. access address. Count Enable Counter 1 disabled for watch point events. Enables/disables the counter for watch Counter 1 enabled for watch point events. point events. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-33...
Page 202: Class Watch Point Access Configuration Register (Cnwpacr)
Defines the optimize access type to Optimized access. monitor. Test Access Non-test access. Defines the test access type to monitor. Test access. Supervisor Access Non-supervisor access. Defines the supervisor access type to Supervisor access. monitor. MSC8144E Reference Manual, Rev. 3 4-34 Freescale Semiconductor...
Page 203 For every bit in CnWPAMR[ADDM] that is cleared, make sure the corresponding bit is cleared in the ADDR. The bit location in ADDM (b) corresponds to the b + 12 bit location in ADDR. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-35...
Page 204: Class Watch Point Extended Access Configuration Register
0xC M3 controller 0xD DDR controller CCSR PCI controller For CLASS2: M2 port 0 M2 port 1 M2 port 2 M2 port 3 0xC M3 controller 0xD DDR controller CCSR PCI controller MSC8144E Reference Manual, Rev. 3 4-36 Freescale Semiconductor...
Page 205 11 Priority 3 (lowest) Byte Count The byte count to monitor can be from 1 to 511 8–0 This field defines the value of the byte bytes. count that the watch point unit monitors. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-37...
Page 206: Class Watch Point Address Mask Registers (Cnwpamr)
11111110 Aligned with a range of 8 KB. sure the corresponding 11111111 Aligned with a range of 4 KB. bit is cleared in the All other values are reserved. CnWPACR. MSC8144E Reference Manual, Rev. 3 4-38 Freescale Semiconductor...
Page 207: Class Profiling Time-Out Registers (Cnptor)
Table 4-21 lists the CnPTOR bit field descriptions. Table 4-21. CnPTOR Bit Descriptions Name Reset Description 0xFFFFFFFF Time-Out 31–0 Holds the time-out value used to stop the profiling unit when the time-out function is enabled. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-39...
Page 208: Class Target Watch Point Control Registers (Cntwpcr)
The targets of the three CLASS modules are as follows: CLASS0 — Target 1 is M2 port 0 — Target 2 is M2 port 1 — Target 3 is M2 port 2 — Target 4 is M2 port 3 MSC8144E Reference Manual, Rev. 3 4-40 Freescale Semiconductor...
Page 209: Class Profiling Irq Status Register (Cnpisr)
Enables monitoring of access by the Watch point event captured. associated target. Overflow Event No overflow occurred. Enables monitoring of access by the CnPRCR overflowed (reached 0xFFFFFFFF) associated target. during the last measurement. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-41...
Page 210: Class Profiling Irq Enable Register (Cnpier)
Overflow interrupt is masked. Enables/disables an overflow interrupt. Overflow interrupt is enabled. 4.7.22 CLASS Profiling Reference Counter Register (CnPRCR) C0PRCR CLASS Profiling Reference Counter Registers Offset 0xE40 C1PRCR C2PRCR Type Reset Type Reset MSC8144E Reference Manual, Rev. 3 4-42 Freescale Semiconductor...
Page 211: Class Profiling General Counter Registers (Cnpgcrx)
Table 4-26. CnPGCR Bit Descriptions Name Reset Description Counter 31–0 Holds the counter value of the selected measurement. Table 4-2 lists the measurements counted by each counter for each configuration combination. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-43...
Page 212: Class General Purpose Register (Cngpr)
PCI subsystem internal which the PCI functions as an initiator only (inbound pipeline enabled. windows disabled and PCICCR[MEM] = 0). MSC8144E Reference Manual, Rev. 3 4-44 Freescale Semiconductor...
Page 213: Class Arbitration Control Register (Cnacr)
— Target 3 is M2 port 2 — Target 4 is M2 port 3 CLASS1 — Target 0 is the CCSR — Target 1 is the DDR controller — Target 2 is the M3 memory MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-45...
Page 214: Class1 Start Address Decoder X (C1Sadx)
The 24 msb of the start address of the specified port window. The lsbs are all zeros. Note: Never write to these registers when there are open transactions being handled by the CLASS to the specified target controlled by the register. MSC8144E Reference Manual, Rev. 3 4-46 Freescale Semiconductor...
Page 215: Class1 End Address Decoder X (C1Eadx)
If the end address is equal to the start address, the window size is 4 Kbytes. Note: Never write to these registers when there are open transactions being handled by the CLASS to the specified target controlled by the register. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 4-47...
Page 216: Class1 Attributes Decoder X (C1Atdx)
Disables the decoder. Enables/disables the specified decoder. Enables the decoder. Note: Never write to these registers when there are open transactions being handled by the CLASS to the specified target controlled by the register. MSC8144E Reference Manual, Rev. 3 4-48 Freescale Semiconductor...
Page 217: Reset
Most of these features are configured by loading reset configuration words to the MSC8144E device that combine with a few direct configuration inputs sampled during the reset sequence. This section describes the various ways to reset and configure the MSC8144E device.
Page 218: Reset Sources
Hard reset (HRESET) This is a bidirectional I/O pin. The MSC8144E can detect an external assertion of HRESET only if it occurs while the MSC8144E is not asserting reset. During HRESET, SRESET is asserted.
Page 219: Power-On Reset Flow
Initially, the reset configuration inputs are sampled to determine the CLKIN configuration source and the input clock division mode. Next, the MSC8144E starts loading the reset configuration words. When the clock mode values in the reset configuration word low load, the system PLL (PLL0) begins to lock.
Page 220: Detailed Power-On Reset Flow
The PCI and RapidIO interfaces are ready to accept external requests, if enabled, and the core boot vector fetch can proceed, if enabled. The MSC8144E is now in its ready state. Figure 5-1 shows a timing diagram of the power-on reset flow. If the reset flow is stopped when...
Page 221 End loading reset configuration words. Start loading reset Resumed loading RCW Duration depends on configuration words source RC_LDF Asserted for half CLKIN cycle Figure 5-2. Resumed Power-On Reset Flow after RC_LDF Is Asserted MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 222: Hreset Flow
Figure 5-3. Hard Reset Flow Note: Because the MSC8144E does not sample the reset configuration signals during a hard reset flow, changing the levels of these signals from the values samples during a sequence has no effect. HRESET 5.1.6 SRESET Flow...
Page 223: Reset Configuration
HRESET PORESET drivers connected to these signals must be tri-stated. Refer to the MSC8144E Technical Data sheet for the recommended resistor values used to pull reset configuration signals high or low. The values loaded from these sampled inputs are accessible to software through memory-mapped registers described in Section 5.3.3.
Page 224: Clkin Frequency Range Signal
HRESET HRESET The MSC8144E resumes reading the RCW; the flow may repeat itself until no error id is detected. This signal can help debug reset issues. 5.2.5 Selecting Reset Configuration Input Signals Table 5-3 shows how to pull down (0) or pull up (1) the reset configuration input signals for various configurations.
Page 225: Reset Configuration Words
Section 5.2.1. 5.2.7.1 Loading From an I C EEPROM When a MSC8144E is configured by the reset input signals to load the reset configuration words from an EEPROM via the I C interface (...
Page 226: Using The Boot Sequencer For Reset Configuration
5.2.7.1.2 EEPROM Addressing A reset initiator MSC8144E is selected by holding the STOP_BS signal low during the power-on reset flow. The reset initiator uses 0b1010000 for the EEPROM calling address. A reset target uses 0b1010111 for the EEPROM calling address. The EEPROM to be addressed must contain the reset configuration information and be programmed to respond to the 0b1010000 address.
Page 227: Loading Multiple Devices From A Single I
During the power on reset assertion, the initiator cannot drive the output bus because its STOP_BS role as initiator is not enabled. Pull-ups are required; refer to the MSC8144E Technical Data sheet for appropriate resistor values to pull the target signal inputs high.
Page 228: Multiple Device External Reset Logic
The multiple device scheme allows ROM code to support a number of devices loading from the same serial EEPROM target. The routine flow is described in Section 6.4.1, Multi Device Support for the I C Bus, on page 6-5. MSC8144E Reference Manual, Rev. 3 5-12 Freescale Semiconductor...
Page 229: Loading Reduced Rcw From External Pins
5.2.7.3 Single Device Loading From I C EEPROM The MSC8144E can be the only device loading the reset configuration word from the I EEPROM. In this case pin must be driven low during the power on and hard reset STOP_BS sequences.
Page 230: Hard Coded Reset Configuration Word High Fields Values
RapidIO prescale timer enable. OCeaN clock is 200 MHz. Reserved. 13-10 0010 for RCW_SRC = 100 Pin multiplexing. 0001 for RCW_SRC = 101 0010 for RCW_SRC = 110 0001 for RCW_SRC = 111 000000 Device ID No reset extension. MSC8144E Reference Manual, Rev. 3 5-14 Freescale Semiconductor...
Page 231: External Reset Configuration Word Low
Select system PLL (PLL0) for PCI. Select system PLL (PLL0) for DDR Select global PLL (PLL2) for M3 reserved. Enable global PLL (PLL2). Enable core PLL (PLL1) Enable system PLL (PLL0) MODCK[5–3]. RC[2–0] MODCK[2–0]. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 5-15...
Page 232: External Reset Configuration Word High Fields Values
RapidIO prescale timer enabled. OCeaN clock is 200 MHz. Reserved. 13-12 Pins multiplexing[3–2]. 11–10 RC[11–10] Pins multiplexing[1–0]. 9–4 RC[9–4] Device ID. No reset extension. 2–1 No loopback mode on SerDes. Common transport type is Large System. MSC8144E Reference Manual, Rev. 3 5-16 Freescale Semiconductor...
Page 233: Reset Programming Model
29–26 SerDes Filter 200 ppm SerDes digital filter bandwidth Selects the SerDes filter. 600 ppm SerDes digital filter bandwidth — Reserved. Write to zero for future compatibility. RapidIO V Select 1.2 V MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 5-17...
Page 234 Enable core PLL (PLL1)s. Disable core PLL (PLL1)s. System PLL (PLL0) Disable Enable system PLL (PLL0). Disable system PLL (PLL0). MODCK Clock Mode See Chapter 7, Clocks. 5–0 Defines the clock operating mode. MSC8144E Reference Manual, Rev. 3 5-18 Freescale Semiconductor...
Page 235: Reset Configuration Word High Register (Rcwhr)
Settings — Reserved. Write to zero for future compatibility. Reset Initiator Configure Targets Reset target. This bit must be set for single MSC8144E device Reset initiator. loading of the RCW from an I C EEPROM and BPRT is I C. See Chapter 6, Boot Program. The number of reset targets is defined externally.
Page 236 RGMII 010010 010011 SGMII Ethernet1 and I 010100 SMII 010101 RMII 010110 RGMII 010111 011000 SGMII (default) 011001... Reserved 111111 Note: When SGMII is selected, make sure that RCWLR[1x] is cleared (0). MSC8144E Reference Manual, Rev. 3 5-20 Freescale Semiconductor...
Page 237: Reset Status Register (Rsr)
Indicates whether the I C boot sequencer failed Boot sequencer failed. while loading the reset configuration words. The bit is cleared by writing a 1 to it; writing zero has no effect. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 5-21...
Page 238 A hard reset event was detected. detected, HRS is set and it remains set until software clears it. HRS is cleared by writing a 1 to it; writing zero has no effect. MSC8144E Reference Manual, Rev. 3 5-22 Freescale Semiconductor...
Page 239: Reset Protection Register (Rpr)
0x52535445 (“RSTE” in ASCII) to the RCPW to enable the RCR. When the RCR is enabled, the RCER[CRE] bit is set. Reading the RPR always returns all zeros. To disable write to the RCR, write a 1 to RCER[CRE]. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 5-23...
Page 240: Reset Control Register (Rcr)
0. SWHR Software Hard Reset Normal operation. Setting this bit cause the MSC8144E to begin a Initiates a hard reset. hard reset flow. This bit returns to its reset state during the reset sequence, so reading it always returns a 0.
Page 241: Reset Control Enable Register (Rcer)
The enable value is written to the reset (RCR). Writing 1 to this bit disables the RCR protection register (RPR) to enable the RCR. and clears this bit. Writing zero has no effect. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 5-25...
Page 242 Reset MSC8144E Reference Manual, Rev. 3 5-26 Freescale Semiconductor...
Page 243: Boot Program
Boot Program The boot program initializes the MSC8144E after it completes a reset sequence. The MSC8144E can boot from an external host through the PCI or RapidIO interface or download a user boot program through the I C, SPI, or Ethernet ports. The default boot code is located in an internal 96 KB ROM at 0xFEF00000–0xFEF17FFF and is accessible to all cores.
Page 244: Functional Description
M3 initialization, and then allows the bootloader to place code in the M3 memory. Boot mode select (core 0). This part includes downloading of code from one of the MSC8144E bootable ports as defined by the RCWHR[BPRT] field. Boot completion. All cores complete the boot operation and jump to a user-specified address.
Page 245: Private Configuration
M3 controller has finished its initialization and the M3 memory is accessible. If M3 does not exist in the system, the core disables the T2 port of CLASS1 disabling accesses towards M3. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 246: Shared Configuration
RapidIO lanes. — If RCWLR[1X] is set, 1x is forced on the RapidIO interface (P0CCSR) QUICC Engine module priority is set to be 1 with emergency not masked (that is SDMR[EB1_PR] = 01). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 247: Multi Device Support For The I C Bus
C Bus The MSC8144E can share the I C EEPROM device with other MSC8144E devices for loading the reset configuration word (RCW), as well as for reading configuration during boot loading and execution. When the bus is shared, the bus must distinguish among reset masters, reset slaves,...
Page 248: Example Configuration
If there are more than 5 slaves, GPIO[21] is used to latch the values of GPIO[0–3] into the decoder glue logic (latch when high). This value indicates which of the slave STOP_BS signals to pull low. When an all 1 values are latched, all STOP_BS signals should be pulled high. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 249 Shared Configuration MSC8144E Device 0 RCW_SRC C EPROM CFG_CLKIN_RNG Reset Logic SRESET A[0–2] HRESET Decoder GPIO PORESET STOP_BS MSC8144E Device 1 RCW_SRC CFG_CLKIN_RNG SRESET HRESET PORESET STOP_BS Figure 6-2. I C Multi Device System MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 250 2. Drive corresponding slave RCWs 3. Disable time out counter RCWHR[BPRC] = I2C Last Slave? STOP_BS == 1 RCWHR[BPRC] = I2C All STOP_BS == 1 End of flow Figure 6-3. I C initialization and Multi Device Support MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 251 STOP_BS signals. If the MSC8144E is a an EEPROM slave, the boot waits until STOP_BS is to pulled high before continuing with the boot program, thus allowing all reset slaves to read their reset word before any device tries to access the EEPROM for boot code.
Page 252: Boot Modes
0x000–0x20F must be valid. 64 6 ⋅ ⁄ 2 4 ⋅ 1.48 pairs is the amount that fits in the same space as 64 MAC addresses ( MSC8144E Reference Manual, Rev. 3 6-10 Freescale Semiconductor...
Page 253 Reset Configuration Word Low [31–24] Reset Configuration Word Low of Slave 15 0x0083 Reset Configuration Word Low [23–16] 0x0084 Reset Configuration Word Low [15–8] 0x0085 Reset Configuration Word Low [7–0] Figure 6-4. EEPROM Contents MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 6-11...
Page 254 CODE Checksum[15–8] Checksum and Checksum Checksum[7–0] Checksum[15–8] Checksum[7–0] Block Control (Block #1) ....End of EEPROM Note: The value shown for Block Control is an example only. Figure 6-4. EEPROM Contents (Continued) MSC8144E Reference Manual, Rev. 3 6-12 Freescale Semiconductor...
Page 255 Destination Address. The address to which the payload data should be written. Payload Data. Holds up to 2 bytes (16 Mbytes) of data to be written to on-device memory according to the destination address. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 6-13...
Page 256: Ethernet
Figure 6-6. I C Read Access 6.5.2 Ethernet The MSC8144E device can load files through the Ethernet port using DHCP (Dynamic Host Configuration Protocol) and TFTP (Trivial File Transfer Protocol). Supports RGMII and SGMII @1000 Mbps full duplex connected to a SWITCH (MAC-to-MAC).
Page 257 Reading a block of the boot file, in S-Record format, from a TFTP server. Processing each TFTP data block and placing it in its memory destination. Sending a TFTP acknowledge to the TFTP server. Repeating steps 2–5 until the end of the data is transferred. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 6-15...
Page 258: Dhcp Client
The DHCP server confirms that the IP address has been allocated to the client by returning a DHCPACK unicast message to the client. There are two possibilities for setting the MSC8144E MAC address during the boot: User defined and read from an I C EEPROM.
Page 259: Tftp Client
The S-Record file structure is describes in Figure 6-10. Start Record Data Record 1 Data Record 2 Data Record n End Record Figure 6-10. S-Record file structure MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 6-17...
Page 260 The S0 record is comprised as follows: S0. Indicating it is a starting record. 03. Hexadecimal 03 (decimal 3). Indicating that three character pairs (or ASCII bytes) follow. 0000. Information string (ignored) FC. Checksum field. MSC8144E Reference Manual, Rev. 3 6-18 Freescale Semiconductor...
Page 261: Serial Rapidio Interconnect
MSC8122. Core 0 moves the data to this address. Note: Because the MSC8144E uses 32-bit addressing, use of S3 and S7 is recommended. 6.5.3 Serial RapidIO Interconnect In this procedure a Serial RapidIO master waits for the MSC8122 boot program to finish its default initialization and then initializes the device by typically loading code and data to the on device memory.
Page 262: Pci
Inbound window 0 maps a window of 512 KB starting at address 0xC0000000 which consists of the entire M2 address space. Inbound window 1 maps the a window of 16 MB starting at address 0xD0000000 which consists of the entire M3 address space. MSC8144E Reference Manual, Rev. 3 6-20 Freescale Semiconductor...
Page 263: Spi
0x17171717 to address 0xC007B000 and enables the PCI by clearing the lock bit of the PCI Function Configuration Register. Once the PCIs on all the MSC8144E devices on board are enabled, the PCI host can either numerate the address space as is, or reconfigure some of the inbound window sizes by using the hard-wired window that grants access to the CCSR space prior to numeration.
Page 264: System After Boot
Lost arbitration on I C bus. 0x0027EFFD Time-out on I C acknowledge (9th clock). 0x0027EFFC Stuck SDA (I C bus). 0x00000000 Unexpected debug condition in the SC3400 Core (unexpected interrupt, EE0 asserted and so on) MSC8144E Reference Manual, Rev. 3 6-22 Freescale Semiconductor...
Page 265 SerDes PLL = SerDes Clock Serial RapidIO_REF_CLK SERDESCLK serdes PLL Note: The source for CLKOUT is selected at reset via the Reset Configuration Word (RCW). See Chapter 5, Reset for details. Figure 7-1. MSC8144E Clock Scheme MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 266 Clocks MSC8144E clock mapping is listed in Table 7-1. Table 7-1. MSC8144E Clock Mapping Divider Used Clock Name Select Select = 0 Select = 1 CLASS128 CLASS64 QUICC Engine RISC Core0 PCMR1[SYNCLK] Core1 PCMR1[SYNCLK] Core2 PCMR1[SYNCLK] Core3 PCMR1[SYNCLK] PCMR0[GP_CTL2] PCMR0[GP_CTL1]...
Page 267: Clock Control Logic
Table 7-4, Table 7-5, and Table 7-6. The clock circuits are locked by the time that the first stage of the reset configuration is complete (see Chapter 5, Reset for details). Table 7-2. Clock Modes (PLL0) PCMR0 MODE INPRNG EQ DLY MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 268 Clocks Table 7-2. Clock Modes (PLL0) (Continued) PCMR0 MODE INPRNG EQ DLY MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 269 Clock Control Logic Table 7-3. Clock Modes (PLL1) PCMR1 MODE SYNCLK EQ DLY MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 270 Clocks Table 7-3. Clock Modes (PLL1) (Continued) PCMR1 MODE SYNCLK EQ DLY Table 7-4. Clock Modes (PLL2) PCMR2 MODE EQ DLY MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 271 Clock Control Logic Table 7-4. Clock Modes (PLL2) (Continued) PCMR2 MODE EQ DLY MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 272 Clocks Table 7-5. Clock Modes (Dividers for Clocks 0–7) MODE CK0DF CK1DF CK2DF CK3DF CK4DF CK5DF CK6DF CK7DF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 273 Clock Control Logic Table 7-5. Clock Modes (Dividers for Clocks 0–7) (Continued) MODE CK0DF CK1DF CK2DF CK3DF CK4DF CK5DF CK6DF CK7DF Table 7-6. Clock Modes (Dividers for Clocks 8–12) MODE CK8DF CK9DF CK10DF CK11DF CK12DF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 274 Clocks Table 7-6. Clock Modes (Dividers for Clocks 8–12) (Continued) MODE CK8DF CK9DF CK10DF CK11DF CK12DF MSC8144E Reference Manual, Rev. 3 7-10 Freescale Semiconductor...
Page 275: Clock Locking
( HRESET ) for several cycles after has started oscillating again. There is no SRESET CLKIN CLKOUT restriction regarding during relock. PORESET MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-11...
Page 276: Clock Programming Model
Do not relock clocks. Setting this bit initiates PLL clock relocking Relock clocks. according to the clock mode programmed in PCMRs and PAMRs. You must clear the bit after clock relocking is complete MSC8144E Reference Manual, Rev. 3 7-12 Freescale Semiconductor...
Page 277 Used to disable clock 11 to conserve power. Clock 11 disabled. CLK12DIS Clock 12 Disable Clock 12 enabled. Used to disable clock 12 to conserve power. Clock 12 disabled. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-13...
Page 278: Pll Clock Mode Register 0 (Pcmr0B/Pcmr0F)
01101 MF = 14. 11101 MF = 30. 01110 MF = 15. 11110 MF = 31. 01111 MF = 16. 11111 MF = 32. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 7-14 Freescale Semiconductor...
Page 279 17–3 GP_CTL General-Purpose Control Clock source is PLL2 2–0 These bits reflect the value of RCWLR[12–10]. Clock source is PLL0 They control the clock multiplexing of the PCI, DDR, and M3 memory. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-15...
Page 280: Pll Clock Mode Register 1 (Pcmr1B/Pc1Mr1F)
01100 MF = 13. 11100 MF = 29. 01101 MF = 14. 11101 MF = 30. 01110 MF = 15. 11110 MF = 31. 01111 MF = 16. 11111 MF = 32. MSC8144E Reference Manual, Rev. 3 7-16 Freescale Semiconductor...
Page 281 Determines the type of feedback loop used by positive-edge aligned to CLKIN with the PLL. non-zero delay. Use equivalent delay path. System clocks are positive-edge aligned to CLKIN with zero delay. — Reserved. 17–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-17...
Page 282: Pll Clock Mode Register 2 (Pcmr2B/Pcmr2F)
01101 MF = 14. 11101 MF = 30. 01110 MF = 15. 11110 MF = 31. 01111 MF = 16. 11111 MF = 32. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 7-18 Freescale Semiconductor...
Page 283 Determines the type of feedback loop used by positive-edge aligned to CLKIN with the PLL. non-zero delay. Use equivalent delay path. System clocks are positive-edge aligned to CLKIN with zero delay. — Reserved. 17–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-19...
Page 284: Dividers Clock Mode Register 0 (Dcmr0B/Dcmr0F)
0100 CK3DF = 5. 1100 CK3DF = 13. 0101 CK3DF = 6. 1101 CK3DF = 14. 0110 CK3DF = 7. 1110 CK3DF = 15. 0111 CK3DF = 8. 1111 CK3DF = 16. MSC8144E Reference Manual, Rev. 3 7-20 Freescale Semiconductor...
Page 285 0100 CK7DF = 5. 1100 CK7DF = 13. 0101 CK7DF = 6. 1101 CK7DF = 14. 0110 CK7DF = 7. 1110 CK7DF = 15. 0111 CK7DF = 8. 1111 CK7DF = 16. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-21...
Page 286: Dividers Clock Mode Register 1 (Dcmr1B, Dcmr1F)
0100 CK10DF = 5. 1100 CK10DF = 13. 0101 CK10DF = 6. 1101 CK10DF = 14. 0110 CK10DF = 7. 1110 CK10DF = 15. 0111 CK10DF = 8. 1111 CK10DF = 16. MSC8144E Reference Manual, Rev. 3 7-22 Freescale Semiconductor...
Page 287: Pll Auxiliary Mode Register 0 (Pamr0B/Pamr0F)
PAMR0F.The PAMR0 is reset only by a power-on reset. The reset value is determined by the MODCK bits in the reset configuration word low. Settings from this field are used only during relock as defined in Table 7-13 on page 7-25. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-23...
Page 288: Pll Auxiliary Mode Register 1 (Pcmr1B/Pc1Mr1F)
PAMR2F. The reset value is determined by the MODCK bits in the reset configuration word low. Settings from this field are used only during relock as defined in Table 7-13 on page 7-25. MSC8144E Reference Manual, Rev. 3 7-24 Freescale Semiconductor...
Page 289: Values For Reprogramming Clock Modes
0x01301000 0x07300000 0x010BC000 0x03834000 0x038F8000 0x000046FF 0x0000C6FF 0x000046FF 0x01301000 0x07300000 0x028BC000 0x120B4000 0x078F8000 0x000046FF 0x0000C6FF 0x000046FF 0x01301000 0x07300000 0x028BC000 0x120B4000 0x038F8000 0x000046FF 0x0000C6FF 0x000046FF 0x01301000 0x07100000 0x018BC000 0x03834000 0x028F8000 0x000046FF 0x0000C6FF 0x000046FF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 7-25...
Page 290 0x01304000 0x07100000 0x020BC000 0x07034000 0x058F8000 0x000046FF 0x0000C6FF 0x000046FF 0x13713000 0x07000000 0x001FC000 0x00134000 0x001F8000 0x000046FF 0x0000C6FF 0x000046FF 0x25B22000 0x07000000 0x001FC000 0x00134000 0x001F8000 0x000046FF 0x0000C6FF 0x000046FF 0x01301000 0x07000000 0x001FC000 0x008B4000 0x001FC000 0x000046FF 0x0000C6FF 0x000046FF MSC8144E Reference Manual, Rev. 3 7-26 Freescale Semiconductor...
Page 291: General Configuration Registers
General Configuration Registers The MSC8144E device includes a general configuration block that includes thirty-two 32-bit registers. This block provides sets of control and status registers for modules in the device that do not include their own control and status registers.
Page 292: Detailed Register Descriptions
M2 ECC enabled. Disables the ECC in the M2 memory. M2 ECC disabled. — Reserved. Write to 0 for future compatibility. 7–5 TDM_PIPE_LMT 10000 TDM Pipeline Limit 4–0 Specifies the TDM complex pipeline depth. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 293: General Configuration Register 2 (Gcr2)
Core 3 Debug Request No debug request. Asserts a debug request to core 3. Debug request. CORE2_DBG_REQ Core 2 Debug Request No debug request. Asserts a debug request to core 2. Debug request. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 294: General Status Register 1 (Gsr1)
Signal is high signal. — Reserved. Write to 0 for future compatibility. 24–21 L2I_IDLE L2 ICache Status L2 ICache is not in Idle mode. Reflects the L2 ICache status. L2 ICache is in Idle mode. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 295 Core 1 Debug Status Not in Debug mode. Reflects the mode of core 1. In Debug mode. CORE0_DBG_STS Core 0 Debug Status Not in Debug mode. Reflects the mode of core 0. In Debug mode. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 296: Lynx General Configuration Register (L_Gcr)
STOP Type Reset L_GCR controls part of the SERDES operation for the MSC8144E device. The register is reset on a Table 8-4 lists the L_GCR bit Hard reset. Write accesses can only be performed in Supervisor mode. field descriptions. Table 8-4. L_GCR Bit Descriptions...
Page 297: Ddr General Control Register (Ddr_Gcr)
DDR_VSEL Type Reset DDR_GCR controls the DDR operation voltage for the MSC8144E device. The register is reset on a Table 8-5 lists the DDR_GCR Hard reset. Write accesses can only be performed in Supervisor mode. bit field descriptions. Table 8-5. DDR_GCR Bit Descriptions...
Page 298: Rapidio Control Register (Rio_Cr)
Selects peak amplitude. 5/6 V -diff-pk = pk RIO_XMIT_EQ[2–0]3 Equalization Selection No equalization. 6–4 1.09x relative amplitude. 1.2x relative amplitude. 1.33x relative amplitude. 1.5x relative amplitude 1.71x relative amplitude 2.0x relative amplitude Reserved. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 299: Sgmii Control Register (Sgmii_Cr)
Proper External DC Coupling Enable Not enabled. Enables proper DC coupling when external Enabled. coupling is used for SGMII. SGMII_INTACCPL_EN Internal AC Amplifier Coupling Not enabled. Enables internal AC amplifier coupling for Enabled. SGMII. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 300: Quicc Engine Control Register (Qectlr)
UTOPIA Rx is master. UTP_TX_M UTOPIA TX as Master UTOPIA Tx not master. Configures the UTOPIA Tx pins as master. UTOPIA Tx is master. — Reserved. Write to 0 for future compatibility. 9–8 MSC8144E Reference Manual, Rev. 3 8-10 Freescale Semiconductor...
Page 301: Gpio Input Enable Register (Gier)
Table 8-9. GIER Bit Descriptions Name Reset Description Settings IE[31–0] Input Enable 31–0 Input is disabled. 31–0 Each bit in this field enables/disables the Input is enabled. individual I/O signals corresponding to the bit index number. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 8-11...
Page 302: System Part And Revision Id Register (Spridr)
Table 8-10. SPRIDR Bit Descriptions for Mask Set M31H Name Reset Description Settings PARTID Part Identification 0x1807 31–16 Mask programmed to indicate the device number. REVID Revision Identification 0x0020 15–0 Mask programmed with the revision number for this part. MSC8144E Reference Manual, Rev. 3 8-12 Freescale Semiconductor...
Page 303: General Configuration Register 4 (Gcr4)
11 Three delay units. UCC3TXDD UCC3 TX Data Delay 00 No delay. 11–10 Adds a delay to the specified signal. 01 One delay unit. 10 Two delay units. 11 Three delay units. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 8-13...
Page 304: General Interrupt Register 1 (Gir1)
8.2.12 General Interrupt Register 1 (GIR1) GIR1 General Interrupt Register 1 Offset 0x40 — Type Reset — Type Reset — VNMI_3 VNMI_2 VNMI_1 VNMI_0 Type Reset — M2_3_ECC M2_2_ECC M2_1_ECC M2_0_ECC Type Reset MSC8144E Reference Manual, Rev. 3 8-14 Freescale Semiconductor...
Page 305 Interrupt not asserted Asserted when ECC error is reported by M2_1 Interrupt asserted M2_0_ECC M2 Block 0 ECC Error Interrupt Interrupt not asserted Asserted when ECC error is reported by M2_0 Interrupt asserted MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 8-15...
Page 306: General Interrupt Register 1 (Gier1_X)
M2 Block 2 ECC Error Enable Interrupt disabled Interrupt enabled M2_1_ECC_EN M2 Block 1 ECC Error Enable Interrupt disabled Interrupt enabled M2_0_ECC_EN M2 Block 0 ECC Error Enable Interrupt disabled Interrupt enabled MSC8144E Reference Manual, Rev. 3 8-16 Freescale Semiconductor...
Page 307: General Interrupt Register 2 (Gir2)
Type Reset GIR2 includes interrupt status of some events within MSC8144E that are rare. Those bits are not sticky but only sample the events. The GIR2 register is reset on a hard reset event. All bits will be deasserted on reset Table 8-14.
Page 308 Interrupt asserted TDM0_TERR TDM0 Transmit Error Interrupt Interrupt not asserted Reflects TDM0 Transmit error interrupt Interrupt asserted TDM0_RERR TDM0 Receive Error Interrupt Interrupt not asserted Reflects TDM0 Receive error interrupt Interrupt asserted MSC8144E Reference Manual, Rev. 3 8-18 Freescale Semiconductor...
Page 309: General Interrupt Enable Register 2 (Gier2_X)
SWT 1 Interrupt Enable Interrupt disabled Interrupt enabled SWT0_EN SWT 0 Interrupt Enable Interrupt disabled Interrupt enabled OCN_ERR_EN OCeaN Error Interrupt Enable Interrupt disabled Interrupt enabled PCI_ERR_EN PCI Error Interrupt Enable Interrupt disabled Interrupt enabled MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 8-19...
Page 310 Interrupt enabled TDM1_TERR_EN TDM1 Transmit Error Interrupt Enable Interrupt disabled Interrupt enabled TDM1_RERR_EN TDM1 Receive Error Interrupt Enable Interrupt disabled Interrupt enabled TDM0_TERR_EN TDM0 Transmit Error Interrupt Enable Interrupt disabled Interrupt enabled MSC8144E Reference Manual, Rev. 3 8-20 Freescale Semiconductor...
Page 311: General Interrupt Register 3 (Gir3)
CLS0_OV Type Reset GIR3 includes interrupt status of some debug/profiling events within MSC8144E. Those bits are not sticky but only sample the events. The GIR3 register is reset by a hard reset event. All bits are cleared on reset Table 8-16. GIR2 Bit Descriptions...
Page 312: General Interrupt Enable Register 3 (Gier3_X)
Type Reset — — — — — — — — Type Reset — — — — PM_EN L2ICS_WP_EN L2ICS_OV_EN L2ICM_WP_EN Type Reset L2ICM_OV_EN CLS2_WP_EN CLS2_OV_EN CLS1_ERR_EN CLS1_WP_EN CLS1_OV_EN CLS0_WP_EN CLS0_OV_EN Type Reset MSC8144E Reference Manual, Rev. 3 8-22 Freescale Semiconductor...
Page 313 Detailed Register Descriptions GIER3_[0–3] include interrupt enable bits for cores 0–3 for debug/profiling events within MSC8144E. GIER3_[0–3] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can be performed only in supervisor mode Table 8-17.
Page 314 General Configuration Registers MSC8144E Reference Manual, Rev. 3 8-24 Freescale Semiconductor...
Page 315: Memory Map
Memory Map This section describes the memory map of MSC8144E. The MSC8144E incorporates five address spaces: Shared memory (M2, M3, DDR, PCI, QUICC Engine subsystem, and boot ROM) address space. SC3400 DSP core subsystem internal address space is accessible only by the SC3400 core.
Page 316: Sc3400 Dsp Core Subsystem Internal Address Space
The PCI address space size includes 4 GB for PCI memory space, 4 GB for PCI I/O space, and also 256-byte sections of PCI configuration space. The MSC8144E initiators can access all of the PCI addresses using the defined 128 MB window with the help of the PCI outbound windows.
Page 317: Ccsr Address Space
144 K 9.4 CCSR Address Space The MSC8144E CCSR is mapped within a contiguous block of memory. The size of the CCSR in MSC8144E is 956 KB. Table 9-4 details the CCSR address space. Table 9-4. CCSR Address Space...
Page 318 16 K FFF50000–FFF77FFF Reserved 160 K FFF78000–FFF7807F General Configuration Registers FFF78080–FFF79FFF Reserved 8 K – 128 FFF7A000–FFF7A1FF PCI Registers FFF7A200–FFF7EFFF Reserved 20 K – 512 FFF7F000–FFF7F03F UART Registers FFF7F040–FFF7FFFF Reserved 4 K – 64 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 319: L2 Icache Address Space
128 K 9.5 L2 ICache Address Space The MSC8144E L2 ICache address space is divided into two sections: cacheable and non-cacheable. It is accessible only by the instruction bus interface of each of the SC3400 DSP core subsystems. The address space in the range of 0x00000000–0xFFFFFFFF can be divided into two zones (cacheable and non-cacheable) dynamically by programming the L2 ICache.
Page 320: Peripherals View Of The System Address Space
Reserved 9.7 Peripherals View of the System Address Space Table 9-7 describes the system address space as seen by the MSC8144E peripherals (RapidIO, JTAG, QUICC Engine subsystem, TDM, DMA–both MBus interfaces). Table 9-7. Peripherals View of the System Address Space...
Page 321: Consolidated Memory Map
CCSR Address Space 956K FFFFF000–FFFFFFFF Reserved An external initiator (to the MSC8144E device) can generate accesses to the system address space using the PCI inbound address translation. Note: To guarantee normal operation of the device, you cannot program the inbound and outbound windows of the PCI so that they overlap.
Page 322 QUICC Engine Virtual Task Event Register CEVTER − 0xFEE00134 QUICC Engine Virtual Task Mask Register CEVTMR − 0xFEE00138 QUICC Engine RAM Control Register CERCR − 0xFEE0013C– reserved 0xFEE001B7 − 0xFEE001B8 QUICC Engine Microcode Revision Number Register CEURNR MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 323 UCC 1 Receive FIFO Emergency Threshold URFET1 − 0xFEE0202A UCC 1 Receive FIFO Special Emergency Threshold URFSET1 − 0xFEE0202C UCC 1 Transmit FIFO Base UTFB1 − 0xFEE02030 UCC 1 Transmit FIFO Size UTFS1 − 0xFEE02032– reserved 0xFEE02033 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 324 Ethernet 1 Tx 65- to 127-byte Frames E1TX127 − 0xFEE02188 Ethernet 1 Tx 128- to 255-byte Frames E1TX255 − 0xFEE0218C Ethernet 1 Rx 64-byte Frames E1RX64 − 0xFEE02190 Ethernet 1 Rx 65- to 127-byte Frames E1RX127 MSC8144E Reference Manual, Rev. 3 9-10 Freescale Semiconductor...
Page 325 − 0xFEE02238 UCC 3 Transmit FIFO Transmit Threshold UTFTT3 − 0xFEE0223A– reserved 0xFEE0223B − 0xFEE0223C UCC 3 Transmit Polling Timer UFPT3 − 0xFEE0223E– reserved 0xFEE0223F − 0xFEE02240 UCC 3 Retry Counter URTRY3 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-11...
Page 326 Ethernet 2 Multicast Frame Transmitted OK E2TMCA − 0xFEE023A4 Ethernet 2 Broadcast Frames Transmitted OK E2TBCA − 0xFEE023A8 Ethernet 2 Number of Frames Received OK E2RXFOK − 0xFEE023AC Ethernet 2 Rx Octets OK E2RBYT MSC8144E Reference Manual, Rev. 3 9-12 Freescale Semiconductor...
Page 327 UCC 5 Retry Counter URTRY5 − 0xFEE02444– reserved 0xFEE0248F − 0xFEE02490 UCC 5 General Extended Mode Register GUEMR5 − 0xFEE02494– reserved 0xFEE027FF − 0xFEE02800 MIIGSK Configuration Register 1 MIIGSK1_CFGR − 0xFEE02804– reserved 0xFEE02807 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-13...
Page 328 UPC Device 1 Receive Port Priority Register UPDRP1 − 0xFEE02E54– reserved 0xFEE02E5F − 0xFEE02E60 UPC Device 1 Event UPDE1 − 0xFEE02E64– reserved 0xFEE02E6F − 0xFEE02E70 UPC Device 1 Internal Rate Configuration Register UPRP1 MSC8144E Reference Manual, Rev. 3 9-14 Freescale Semiconductor...
Page 329 − 0xFEE08000– RAM space reserved 0xFEE0FFFF − 0xFEE10000– Multi-User RAM 0xFEE1BFFF − 0xFEE1C000– reserved 0xFEE3FFFF • 0xFEE40000– reserved (for QUICC Engine subsystem) 0xFEEFFFFF • 0xFEF00000– Boot ROM 0xFEF17FFF • 0xFEF18000– reserved 0xFEFFFFFF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-15...
Page 330 EDCA1 Reference Value B EDCA1_REFB OCE RM − 0xFFEFFE88 EDCA2 Reference Value B EDCA2_REFB OCE RM − 0xFFEFFE8C EDCA3 Reference Value B EDCA3_REFB OCE RM − 0xFFEFFE90 EDCA4 Reference Value B EDCA4_REFB OCE RM MSC8144E Reference Manual, Rev. 3 9-16 Freescale Semiconductor...
Page 331 TB_CTRL OCE RM − 0xFFEFFF44 Trace Buffer Read Pointer TB_RD OCE RM − 0xFFEFFF48 Trace Buffer Write Pointer TB_WR OCE RM − 0xFFEFFF4C Trace Buffer TB_BUFF OCE RM − 0xFFEFFF50– reserved 0xFFEFFFF7 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-17...
Page 332 EPIC Interrupt priority level Register 24 P_IPL24 − 0xFFF00464 EPIC Interrupt priority level Register 25 P_IPL25 − 0xFFF00468 EPIC Interrupt priority level Register 26 P_IPL26 − 0xFFF0046C EPIC Interrupt priority level Register 27 P_IPL27 MSC8144E Reference Manual, Rev. 3 9-18 Freescale Semiconductor...
Page 333 EPIC Interrupt priority level Register 58 P_IPL58 − 0xFFF004EC EPIC Interrupt priority level Register 59 P_IPL59 − 0xFFF004F0 EPIC Interrupt priority level Register 60 P_IPL60 − 0xFFF004F4 EPIC Interrupt priority level Register 61 P_IPL61 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-19...
Page 334 Data Cache Extended Tag State Register DC_ET − 0xFFF00828 Data Cache Valid Dirty State Register DC_VD − 0xFFF0082C Data Cache Debug Data Register DC_DBG_DATA − 0xFFF00830 Data Cache Debug Access Register DC_DBG_ACS MSC8144E Reference Manual, Rev. 3 9-20 Freescale Semiconductor...
Page 335 MMU Current Data ID Register M_CDID − 0xFFF06108 MMU Data Query Status Register M_DQSR − 0xFFF0610C MMU Data Query Physical Register M_DQPR − 0xFFF06010– reserved 0xFFF06FFF − 0xFFF07000 MMU Program Segment Descriptor Control Register M_PSDCR MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-21...
Page 336 0xFFF0808F − 0xFFF08090 MMU Program Segment Descriptor Registers A9 M_PSDA9 − 0xFFF08094 MMU Program Segment Descriptor Registers B9 M_PSDB9 − 0xFFF08098– reserved 0xFFF0809F − 0xFFF080A0 MMU Program Segment Descriptor Registers A10 M_PSDA10 MSC8144E Reference Manual, Rev. 3 9-22 Freescale Semiconductor...
Page 337 DPU Counter Triad A Control Register DP_TAC page 25-37 − 0xFFF0A024 DPU Counter Triad B Control Register DP_TBC page 25-40 − 0xFFF0A028– reserved 0xFFF0A02B − 0xFFF0A02C DPU Counter A0 Control Register DP_CA0C page 25-42 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-23...
Page 338 − 0xFFF10008 DMA Buffer Descriptor Base Register 2 DMABDBR2 page 14-24 − 0xFFF1000C DMA Buffer Descriptor Base Register 3 DMABDBR3 page 14-24 − 0xFFF10010 DMA Buffer Descriptor Base Register 4 DMABDBR4 page 14-24 MSC8144E Reference Manual, Rev. 3 9-24 Freescale Semiconductor...
Page 339 DMA Channel Disable Register DMACHDR page 14-28 − 0xFFF10210– Reserved 0xFFF10213 − 0xFFF10214 DMA Channel Freeze Register DMACHFR page 14-29 − 0xFFF10218– Reserved 0xFFF10223 − 0xFFF10224 DMA Channel Defrost Register DMACHDFR page 14-29 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-25...
Page 340 DMA Round Robin Priority Group Update Register DMARRPGUR page 14-40 − 0xFFF10380 DMA Channel Active Status Register DMACHASTR page 14-41 − 0xFFF10384– Reserved 0xFFF10387 − 0xFFF10388 DMA Channel Freeze Status Register DMACHFSTR page 14-41 MSC8144E Reference Manual, Rev. 3 9-26 Freescale Semiconductor...
Page 341 4-20 − 0xFFF18890 CLASS 0 Priority Auto Upgrade Control Register 4 C0PACR4 page 4-20 − 0xFFF18894 CLASS 0 Priority Auto Upgrade Control Register 5 C0PACR5 page 4-20 − 0xFFF18898– reserved 0xFFF189FF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-27...
Page 342 CLASS 0 Target Watch Point Control Register C0TWPCR page 4-40 − 0xFFF18E20 CLASS 0 Profiling IRQ Status Register C0PISR page 4-41 − 0xFFF18E24 CLASS 0 Profiling IRQ Enable Register C0PIER page 4-42 − 0xFFF18E28- Reserved 0xFFF18E3F MSC8144E Reference Manual, Rev. 3 9-28 Freescale Semiconductor...
Page 343 CLASS 1 Priority Auto Upgrade Control Register 1 C1PACR1 page 4-20 − 0xFFF19888 CLASS 1 Priority Auto Upgrade Control Register 2 C1PACR2 page 4-20 − 0xFFF1988C CLASS 1 Priority Auto Upgrade Control Register 3 C1PACR3 page 4-20 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-29...
Page 344 CLASS 1 Arbitration Weight Register 4 C1AWR4 page 4-26 − 0xFFF19A94 CLASS 1 Arbitration Weight Register 5 C1AWR5 page 4-26 − 0xFFF19A98– reserved 0xFFF19C03 − 0xFFF19C04 CLASS 1 Start Address Decoder 1 C1SAD1 page 4-46 MSC8144E Reference Manual, Rev. 3 9-30 Freescale Semiconductor...
Page 345 CLASS 1 Arbitration Control Register C1ACR page 4-45 − 0xFFF19FC4– Reserved 0xFFF19FFF • 0xFFF1A000– CLASS 2 0xFFF1AFFF − 0xFFF1A000 CLASS 2 MBus Target Configuration Register 0 C2MTCR0 page 4-15 − 0xFFF1A004– Reserved 0xFFF1A7FF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-31...
Page 346 C2ISR page 4-27 − 0xFFF1AD84– Reserved 0xFFF1ADBF − 0xFFF1ADC0 CLASS 2 IRQ Enable Register C2IER page 4-28 − 0xFFF1ADC4– Reserved 0xFFF1ADFF − 0xFFF1AE00 CLASS 2 Target Profiling Configuration Register C2TPCR page 4-29 MSC8144E Reference Manual, Rev. 3 9-32 Freescale Semiconductor...
Page 347 TIMING_CFG_0 page 12-35 − 0xFFF20108 DDR SDRAM Timing Configuration 1 TIMING_CFG_1 page 12-38 − 0xFFF2010C DDR SCRAM Timing Configuration 2 TIMING_CFG_2 page 12-40 − 0xFFF20110 DDR SDRAM Control Configuration DDR_SDRAM_CFG page 12-42 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-33...
Page 348 DDR SDRAM MDIC Output Enable Control Register MDIC_OE_CONT page 12-65 − 0xFFF2100C DDR SDRAM Termination, OCD, and ODT Control Register TERM_OCD_ODT_CONT page 12-66 − 0xFFF21010 DDR SDRAM Clock Ratio Control Register CLK_RATIO_CONT page 12-67 MSC8144E Reference Manual, Rev. 3 9-34 Freescale Semiconductor...
Page 349 0xFFF248FF − 0xFFF24800 Reset Configuration Word Low Register RCWLR page 5-17 − 0xFFF24804 Reset Configuration Word High Register RCWHR page 5-19 − 0xFFF24808– reserved 0xFFF2480F − 0xFFF24810 Reset Status Register page 5-21 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-35...
Page 350 System Watchdog 1 Count Register SW1CNR page 21-26 − 0xFFF2510C– reserved 0xFFF2510D − 0xFFF2510E System Watchdog 1 Service Register SW1SRR page 21-27 − 0xFFF25110– reserved 0xFFF251FF • 0xFFF25200– Watchdog Timer 2 0xFFF252FF MSC8144E Reference Manual, Rev. 3 9-36 Freescale Semiconductor...
Page 351 Timer 0 Channel 0 Status and Control Register TMR0SCTL0 page 21-19 − 0xFFF26020 Timer 0 Channel 0 Compare Load 1 Register TMR0CMPLD10 page 21-22 − 0xFFF26024 Timer 0 Channel 0 Compare Load 2 Register TMR0CMPLD20 page 21-22 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-37...
Page 352 21-22 − 0xFFF260E4 Timer 0 Channel 3 Compare Load 2 Register TMR0CMPLD23 page 21-22 − 0xFFF260E8 Timer 0 Channel 3 Comparator Status and Control Register TMR0COMSC3 page 21-22 − 0xFFF260EC– reserved 0xFFF260FF MSC8144E Reference Manual, Rev. 3 9-38 Freescale Semiconductor...
Page 353 Timer 1 Channel 2 Comparator Status and Control Register TMR1COMSC2 page 21-22 − 0xFFF261AC– reserved 0xFFF261BF − 0xFFF261C0 Timer 1 Channel 3 Compare 1 Register TMR1CMP13 page 21-21 − 0xFFF261C4 Timer 1 Channel 3 Compare 2 Register TMR1CMP23 page 21-21 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-39...
Page 354 Timer 2 Channel 2 Compare 2 Register TMR2CMP22 page 21-21 − 0xFFF26288 Timer 2 Channel 2 Capture Register TMR2CAP2 page 21-23 − 0xFFF2628C Timer 2 Channel 2 Load Register TMR2LOAD2 page 21-24 MSC8144E Reference Manual, Rev. 3 9-40 Freescale Semiconductor...
Page 355 − 0xFFF2634C Timer 3 Channel 1 Load Register TMR3LOAD1 page 21-24 − 0xFFF26350 Timer 3 Channel 1 Hold Register TMR3HOLD1 page 21-24 − 0xFFF26354 Timer 3 Channel 1 Counter Register TMR3CNTR1 page 21-24 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-41...
Page 356 • 0xFFF26400– reserved 0xFFF26FFF • 0xFFF27000– 0xFFF270FF − 0xFFF27000 Virtual Interrupt Generation Register VIGR page 13-13 − 0xFFF27004– reserved 0xFFF27007 − 0xFFF27008 Virtual Interrupt Status Register VISR page 13-14 − 0xFFF2700C– reserved 0xFFF2700F MSC8144E Reference Manual, Rev. 3 9-42 Freescale Semiconductor...
Page 357 Pin Data Direction Register PDIR page 22-9 − 0xFFF27214– reserved 0xFFF27217 − 0xFFF27218 Pin Assignment Register page 22-9 − 0xFFF2721C– reserved 0xFFF2721F − 0xFFF27220 Pin Special Options Register PSOR page 22-10 − 0xFFF27224– reserved 0xFFF272FF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-43...
Page 358 TDM0 Receive Channel Parameters Register 0–255 TDM0RCPR[0–255] page 19-62 0xFFF313FC − 0xFFF31400– reserved 0xFFF317FF − 0xFFF31800– TDM0 Transmit Local Memory 0xFFF31FFF − 0xFFF32000– reserved 0xFFF327FF − 0xFFF32800– TDM0 Transmit Channel Parameters Register 0–255 TDM0TCPR[0–255] page 19-63 0xFFF32BFC MSC8144E Reference Manual, Rev. 3 9-44 Freescale Semiconductor...
Page 359 TDM0 Receive Data Buffer Displacement Register TDM0RDBDR page 19-67 − 0xFFF33F64– reserved 0xFFF33F67 − 0xFFF33F68 TDM0 Adaptation Sync Distance Register TDM0ASDR page 19-66 − 0xFFF33F6C– reserved 0xFFF33F6F − 0xFFF33F70 TDM0 Transmit Interrupt Enable Register TDM00TIER page 19-65 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-45...
Page 360 TDM0 Transmit Frame Parameters TDM0TFP page 19-51 − 0xFFF33FDC– reserved 0xFFF33FDF − 0xFFF33FE0 TDM0 Receive Frame Parameters TDM0RFP page 19-48 − 0xFFF33FE4– reserved 0xFFF33FE7 − 0xFFF33FE8 TDM0 Transmit Interface Register TDM0TIR page 19-46 MSC8144E Reference Manual, Rev. 3 9-46 Freescale Semiconductor...
Page 361 19-73 − 0xFFF37F24– reserved 0xFFF37F27 − 0xFFF37F28 TDM1 Receive Status Register TDM1RSR page 19-72 − 0xFFF37F2C– reserved 0xFFF37F2F − 0xFFF37F30 TDM1 Adaptation Status Register TDM1ASR page 19-71 − 0xFFF37F34– reserved 0xFFF37F37 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-47...
Page 362 TDM1 Transmit Control Register TDM1TCR page 19-59 − 0xFFF37FA4– reserved 0xFFF37FA7 − 0xFFF37FA8 TDM1 Receive Control Register TDM1RCR page 19-58 − 0xFFF37FAC– reserved 0xFFF37FAF − 0xFFF37FB0 TDM1 Adaptation Control Register TDM1ACR page 19-57 MSC8144E Reference Manual, Rev. 3 9-48 Freescale Semiconductor...
Page 363 0xFFF393FC − 0xFFF39400– reserved 0xFFF397FF − 0xFFF39800– TDM2 Transmit Local Memory 0xFFF39FFF − 0xFFF3A000– reserved 0xFFF3A7FF − 0xFFF3A800– TDM2 Transmit Channel Parameters Register 0–255 TDM2TCPR[0–255] page 19-63 0xFFF3ABFC − 0xFFF3AC00– reserved 0xFFF3BEFF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-49...
Page 364 TDM2 Adaptation Sync Distance Register TDM2ASDR page 19-66 − 0xFFF3BF6C– reserved 0xFFF3BF6F − 0xFFF3BF70 TDM2 Transmit Interrupt Enable Register TDM20TIER page 19-65 − 0xFFF3BF74– reserved 0xFFF3BF77 − 0xFFF3BF78 TDM2 Receive Interrupt Enable Register TDM2RIER page 19-64 MSC8144E Reference Manual, Rev. 3 9-50 Freescale Semiconductor...
Page 365 19-48 − 0xFFF3BFE4– reserved 0xFFF3BFE7 − 0xFFF3BFE8 TDM2 Transmit Interface Register TDM2TIR page 19-46 − 0xFFF3BFEC– reserved 0xFFF3BFEF − 0xFFF3BFF0 TDM2 Receive Interface Register TDM2RIR page 19-44 − 0xFFF3BFF4– reserved 0xFFF3BFF7 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-51...
Page 366 TDM3 Adaptation Status Register TDM3ASR page 19-71 − 0xFFF3FF34– reserved 0xFFF3FF37 − 0xFFF3FF38 TDM3 Transmit Event Register TDM3TER page 19-70 − 0xFFF3FF3C– reserved 0xFFF3FF3F − 0xFFF3FF40 TDM3 Receive Event Register TDM3RER page 19-69 MSC8144E Reference Manual, Rev. 3 9-52 Freescale Semiconductor...
Page 367 TDM3 Receive Control Register TDM3RCR page 19-58 − 0xFFF3FFAC– reserved 0xFFF3FFAF − 0xFFF3FFB0 TDM3 Adaptation Control Register TDM3ACR page 19-57 − 0xFFF3FFB4– reserved 0xFFF3FFB7 − 0xFFF3FFB8 TDM3 Transmit Global Base Address TDM3TGBA page 19-55 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-53...
Page 368 − 0xFFF42000– reserved 0xFFF427FF − 0xFFF42800– TDM4 Transmit Channel Parameters Register 0–255 TDM4TCPR[0–255] page 19-63 0xFFF42BFC − 0xFFF42C00– reserved 0xFFF43EFF − 0xFFF43F00 TDM4 Parity Control Register TDM4PCR page 19-57 − 0xFFF43F04– reserved 0xFFF43F07 MSC8144E Reference Manual, Rev. 3 9-54 Freescale Semiconductor...
Page 369 TDM40TIER page 19-65 − 0xFFF43F74– reserved 0xFFF43F77 − 0xFFF43F78 TDM4 Receive Interrupt Enable Register TDM4RIER page 19-64 − 0xFFF43F7C– reserved 0xFFF43F7F − 0xFFF43F80 TDM4 Transmit Data Buffer Second Threshold TDM4TDBST page 19-61 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-55...
Page 370 TDM4 Transmit Interface Register TDM4TIR page 19-46 − 0xFFF43FEC– reserved 0xFFF43FEF − 0xFFF43FF0 TDM4 Receive Interface Register TDM4RIR page 19-44 − 0xFFF43FF4– reserved 0xFFF43FF7 − 0xFFF43FF8 TDM4 General Interface Register TDM4GIR page 19-36 MSC8144E Reference Manual, Rev. 3 9-56 Freescale Semiconductor...
Page 371 19-71 − 0xFFF47F34– reserved 0xFFF47F37 − 0xFFF47F38 TDM5 Transmit Event Register TDM5TER page 19-70 − 0xFFF47F3C– reserved 0xFFF47F3F − 0xFFF47F40 TDM5 Receive Event Register TDM5RER page 19-69 − 0xFFF47F44– reserved 0xFFF47F47 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-57...
Page 372 TDM5 Adaptation Control Register TDM5ACR page 19-57 − 0xFFF47FB4– reserved 0xFFF47FB7 − 0xFFF47FB8 TDM5 Transmit Global Base Address TDM5TGBA page 19-55 − 0xFFF47FBC– reserved 0xFFF47FBF − 0xFFF47FC0 TDM5 Receive Global Base Address TDM5RGBA page 19-54 MSC8144E Reference Manual, Rev. 3 9-58 Freescale Semiconductor...
Page 373 19-63 0xFFF4ABFC − 0xFFF4AC00– reserved 0xFFF4BEFF − 0xFFF4BF00 TDM6 Parity Control Register TDM6PCR page 19-57 − 0xFFF4BF04– reserved 0xFFF4BF07 − 0xFFF4BF08 TDM6 Parity Error Register TDM6PER page 19-73 − 0xFFF4BF0C– reserved 0xFFF4BF0F MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-59...
Page 374 19-64 − 0xFFF4BF7C– reserved 0xFFF4BF7F − 0xFFF4BF80 TDM6 Transmit Data Buffer Second Threshold TDM6TDBST page 19-61 − 0xFFF4BF84– reserved 0xFFF4BF87 − 0xFFF4BF88 TDM6 Receive Data Buffer Second Threshold TDM6RDBST page 19-61 MSC8144E Reference Manual, Rev. 3 9-60 Freescale Semiconductor...
Page 375: Msc8144E Reference Manual, Rev
0xFFF4BFEF − 0xFFF4BFF0 TDM6 Receive Interface Register TDM6RIR page 19-44 − 0xFFF4BFF4– reserved 0xFFF4BFF7 − 0xFFF4BFF8 TDM6 General Interface Register TDM6GIR page 19-36 − 0xFFF4BFFC– reserved 0xFFF4BFFF • 0xFFF4C000– TDM7 0xFFF4FFFF MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-61...
Page 376 19-70 − 0xFFF4FF3C– reserved 0xFFF4FF3F − 0xFFF4FF40 TDM7 Receive Event Register TDM7RER page 19-69 − 0xFFF4FF44– reserved 0xFFF4FF47 − 0xFFF4FF48 TDM7 Transmit Number of Buffers TDM7TNB page 19-69 − 0xFFF4FF4C– reserved 0xFFF4FF4F MSC8144E Reference Manual, Rev. 3 9-62 Freescale Semiconductor...
Page 377 TDM7 Transmit Global Base Address TDM7TGBA page 19-55 − 0xFFF4FFBC– reserved 0xFFF4FFBF − 0xFFF4FFC0 TDM7 Receive Global Base Address TDM7RGBA page 19-54 − 0xFFF4FFC4– reserved 0xFFF4FFC7 − 0xFFF4FFC8 TDM7 Transmit Data Buffer Size TDM7TDBS page 19-54 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-63...
Page 378 General Interrupt Enable Register 1 for Core 2 GIER1_2 page 8-16 − 0xFFF78050 General Interrupt Enable Register 1 for Core 3 GIER1_3 page 8-16 − 0xFFF78054 General Interrupt Register 2 GIR2 page 8-17 MSC8144E Reference Manual, Rev. 3 9-64 Freescale Semiconductor...
Page 379 PCI Inbound Base Address Register 0 PIBAR0 page 15-41 − 0xFFF7A078 PCI Inbound Window Attribute Register 0 PIWAR0 page 15-41 − 0xFFF7A07C– reserved 0xFFF7A0FF − 0xFFF7A100 PCI Outbound Translation Address Register 0 POTAR0 page 15-43 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-65...
Page 380 15-44 − 0xFFF7A16C– reserved 0xFFF7A16F − 0xFFF7A170 PCI Outbound Comparison Mask Register 4 POCMR4 page 15-44 − 0xFFF7A174– reserved 0xFFF7A177 − 0xFFF7A178 PCI Outbound Translation Address Register 5 POTAR5 page 15-43 MSC8144E Reference Manual, Rev. 3 9-66 Freescale Semiconductor...
Page 381 Destination Operations Capability Register DOCAR page 16-109 − 0xFFF80020– reserved 0xFFF8003F − 0xFFF80040 Mailbox Command And Status Register MCSR page 16-111 − 0xFFF80044 Port -Write and Doorbell Command and Status Register PWDCSR page 16-112 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-67...
Page 382 Register − 0xFFF80610– reserved 0xFFF80613 − 0xFFF80614 Logical/Transport Layer Address Capture Command and LTLACCSR page 16-133 Status Register − 0xFFF80618 Logical/Transport Layer Device ID Capture Command and LTLDIDCCSR page 16-134 Status Register MSC8144E Reference Manual, Rev. 3 9-68 Freescale Semiconductor...
Page 383 Register − 0xFFF90128– reserved 0xFFF9012F − 0xFFF90130 Port 0 Implementation Error Command and Status Register P0IECSR page 16-153 − 0xFFF90134– reserved 0xFFF9013F − 0xFFF90140 Port 0 Physical Configuration Register P0PCR page 16-154 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-69...
Page 384 16-158 Register 3 − 0xFFF90C64 Port 0 RapidIO Outbound Window Translation Extended P0ROWTEAR3 page 16-159 Address Register 3 − 0xFFF90C68 Port 0 RapidIO Outbound Window Base Address Register 3 P0ROWBAR3 page 16-162 MSC8144E Reference Manual, Rev. 3 9-70 Freescale Semiconductor...
Page 385 0xFFF90CEF − 0xFFF90CF0 Port 0 RapidIO Outbound Window Attributes Register 7 P0ROWAR7 page 16-160 − 0xFFF90CF4– reserved 0xFFF90CFF − 0xFFF90D00 Port 0 RapidIO Outbound Window Translation Address P0ROWTAR8 page 16-158 Register 8 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-71...
Page 386 16-165 − 0xFFF90DCC– reserved 0xFFF90DCF − 0xFFF90DD0 RapidIO Inbound Window Attributes Register 1 RIWAR1 page 16-166 − 0xFFF90DD4– reserved 0xFFF90DDF − 0xFFF90DE0 RapidIO Inbound Window Translation Address Register 0 RIWTAR0 page 16-164 MSC8144E Reference Manual, Rev. 3 9-72 Freescale Semiconductor...
Page 387 IM0MIRIR page 16-186 Register − 0xFFF9307C– reserved 0xFFF930FF − 0xFFF93100 Outbound Message 1 Mode Register OM1MR page 16-167 − 0xFFF93104 Outbound Message 1 Status Register OM1SR page 16-169 − 0xFFF93108– reserved 0xFFF9310B MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-73...
Page 388 Outbound Doorbell Retry Error Threshold Configuration ODRETCR page 16-191 Register − 0xFFF93430– reserved 0xFFF9345F − 0xFFF93460 Inbound Doorbell Mode Register IDMR page 16-192 − 0xFFF93464 Inbound Doorbell Status Register IDSR page 16-194 MSC8144E Reference Manual, Rev. 3 9-74 Freescale Semiconductor...
Page 389 − 0xFFFA2130 DMA 0 Current List Descriptor Extended Address Register ECLSDAR0 − 0xFFFA2134 DMA 0 Current List Descriptor Address Register CLSDAR0 − 0xFFFA2138 DMA 0 Next List Descriptor Extended Address Register ENLSDAR0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-75...
Page 390 DMA 2 Current List Descriptor Extended Address Register ECLSDAR2 − 0xFFFA2234 DMA 2 Current List Descriptor Address Register CLSDAR2 − 0xFFFA2238 DMA 2 Next List Descriptor Extended Address Register ENLSDAR2 − 0xFFFA223C DMA 2 Next List Descriptor Address Register NLSDAR2 MSC8144E Reference Manual, Rev. 3 9-76 Freescale Semiconductor...
Page 391 Local Access Window Attributes Register 1 LAWAR1 − 0xFFFA3C34– reserved 0xFFFA3C47 − 0xFFFA3C48 Local Access Window Base Address Register 2 LAWBAR2 − 0xFFFA3C4C– reserved 0xFFFA3C4F − 0xFFFA3C50 Local Access Window Attributes Register 2 LAWAR2 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-77...
Page 392 0xFFFA3D27 − 0xFFFA3D28 Local Access Window Base Address Register 9 LAWBAR9 − 0xFFFA3D2C– reserved 0xFFFA3D2F − 0xFFFA3D30 Local Access Window Attributes Register 9 LAWAR9 − 0xFFFA3D34– reserved 0xFFFA3FFF • 0xFFFA4000– reserved 0xFFFC00FF MSC8144E Reference Manual, Rev. 3 9-78 Freescale Semiconductor...
Page 393 0xFFFC017F − 0xFFFC0180 Performance Monitor Local Control Register A7 PMLCA7 page 25-81 − 0xFFFC0184 Performance Monitor Local Control Register B7 PMLCB7 page 25-83 − 0xFFFC0188 Performance Monitor Counter 7 PMC7 page 25-85 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-79...
Page 394 Channel 2 Pointer Status Register CPSR2 page 26-92 − 0xFFFD1218– reserved 0xFFFD123F − 0xFFFD1240 Channel 2 Current Descriptor Pointer Register CDPR2 page 26-98 − 0xFFFD1248 Channel 2 Fetch FIFO CFF2 page 26-99 − 0xFFFD1250– reserved 0xFFFD127F MSC8144E Reference Manual, Rev. 3 9-80 Freescale Semiconductor...
Page 395 26-79 − 0xFFFD1C00– reserved 0xFFFD1FFF − 0xFFFD2000 DEU Mode Register DEUMR page 26-113 − 0xFFFD2008 DEU Key Size Register DEUKSR page 26-114 − 0xFFFD2010 DEU Data Size Register DEUDSR page 26-115 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-81...
Page 396 AESU Context Register 4 AESUCR4 page 26-134 − 0xFFFD4120 AESU Context Register 5 AESUCR5 page 26-134 − 0xFFFD4128 AESU Context Register 6 AESUCR6 page 26-134 − 0xFFFD4130 AESU Context Register 7 AESUCR7 page 26-134 MSC8144E Reference Manual, Rev. 3 9-82 Freescale Semiconductor...
Page 397 26-151 − 0xFFFD8010 AFEU Context/Data Size Register AFEUCDSR page 26-152 − 0xFFFD8018 AFEU Reset Control Register AFEURCR page 26-153 − 0xFFFD8020– reserved 0xFFFD8027 − 0xFFFD8028 AFEU Status Register AFEUSR page 26-154 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-83...
Page 398: Rng Output Fifo
PKEU Mode Register PKEUMR page 26-101 − 0xFFFDC008 PKEU Key Size Register PKEUKSR page 26-103 − 0xFFFDC010 PKEU Data Size Register PKEUDSR page 26-105 − 0xFFFDC018 PKEU Reset Control Register PKEURCR page 26-106 MSC8144E Reference Manual, Rev. 3 9-84 Freescale Semiconductor...
Page 399 0xFFFDE027 − 0xFFFDE028 KEU Status Register KEUSR page 26-166 − 0xFFFDE030 KEU Interrupt Status Register KEUISR page 26-167 − 0xFFFDE038 KEU Interrupt Mask Register KEUIMR page 26-169 − 0xFFFDE040– reserved 0xFFFDE047 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 9-85...
Page 400 26-178 − 0xFFFDE418 KEU Key Data Register 4 KEUKDR4 page 26-178 − 0xFFFDE420– reserved 0xFFFDE7FF − 0xFFFDE800– KEU Input FIFO/Output FIFO — page 26-178 0xFFFDEFFF • 0xFFFDF000– reserved 0xFFFFEFFF 0xFFFFF000– reserved 0xFFFFFFFF MSC8144E Reference Manual, Rev. 3 9-86 Freescale Semiconductor...
Page 401: Msc8144E Sc3400 Dsp Subsystem
Subsystem Reference Manual have detailed information on the DSP core and core subsystem. Both manuals are available with a signed non-disclosure agreement. Contact your local Freescale dealer or sales representative for more information. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 10-1...
Page 402: Sc3400 Dsp Core
— Program bus (P bus) with its address and data buses (PAB, PDB) for fetching program words from memory via the instruction channel to the core Note: See Chapter 2, SC3400 Core Overview and the SC3400 DSP Core Reference Manual for details on the SC3400 core. MSC8144E Reference Manual, Rev. 3 10-2 Freescale Semiconductor...
Page 403: Memory Management Unit (Mmu)
Memory protection is required to increase the reliability of the system, so that errant tasks are not allowed to ruin the privileged state and the state of other tasks. Program and data accesses from MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 404: Instruction Channel
Multi-task support Real-time support through locking flexible boundaries Pre-fetch capability Software coherency support Note: See the MSC8144 SC3400 DSP Core Subsystem Reference Manual for details on the Instruction Channel and the L1 ICache. MSC8144E Reference Manual, Rev. 3 10-4 Freescale Semiconductor...
Page 405: Data Channel And Write Queue
Real-time support through locking flexible boundaries Software coherency support Write-back writing policy Pre-fetch capability Note: See the MSC8144 SC3400 DSP Core Subsystem Reference Manual for details on the Data Channel and the L1 DCache. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 10-5...
Page 406: Interrupt Processing
MMU interrupts, see the MSC8144 SC3400 DSP Core Subsystem Reference Manual. External interrupts. This includes interrupts generated by the MSC8144E internal peripherals and external interrupt input lines. The role of the EPIC module is to manage the interrupt inputs. The EPIC manages the interrupts using a fixed set of priority rules and passes interrupts with the highest priority at any given time to the core.
Page 407 — Generate the PC tracing flow, optionally filtered to a subset of events such as only jumps/returns from subroutine, interrupts, and so forth. See Chapter 25, Debugging, Profiling, and Performance Monitoring for details. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 10-7...
Page 408: Dual Timer
This section describes the DSP core subsystem processing states. These states are related to the SC3400 processing states, but include additional platform-specific attributes. The processing states include: Reset Execution Debug WAIT STOP MSC8144E Reference Manual, Rev. 3 10-8 Freescale Semiconductor...
Page 409: Reset State
(tags, valid bits, PLRU table and cache array) can be read with JTAG-inserted core commands. The state of the cache array could be written to as well. See Chapter 11, Internal Memory Subsystem for details. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 10-9...
Page 410: Wait State
(see Section 8.2.2, General Configuration Register 2 (GCR2), on page 8-3 for details). After setting the bit, the core subsystem does not stop until the corresponding GCR1[COREn_STP_ACK] bit is set (see Section 8.2.3, General Status Register 1 (GSR1), on page 8-4 for details). MSC8144E Reference Manual, Rev. 3 10-10 Freescale Semiconductor...
Page 411: State Transitions
This transition is initiated by the negation of the DSP core subsystem reset input port while the input port is asserted. 10.9.6.3 Transition to Reset State This transition is initiated by the assertion of the DSP core subsystem reset input port in any of the other states. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 10-11...
Page 412: Transition From Execution To Debug State
Debug state and not the Execution state. See Section 10.9.6.8 and Section 10.9.6.9 for details. Please refer to the Emulation and Debug (OCE) chapter in the SC3400 DSP Core Reference Manual for OCE programming details. MSC8144E Reference Manual, Rev. 3 10-12 Freescale Semiconductor...
Page 413: Transition From Stop To Execution State
10.9.6.10 Transition from Debug to Execution State The transition is initiated by the external JTAG controller through its interface to the OCE module. The JTAG controller sets the dedicated exit bit in the OCE command register. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 10-13...
Page 414 MSC8144E SC3400 DSP Subsystem MSC8144E Reference Manual, Rev. 3 10-14 Freescale Semiconductor...
Page 415 For detailed programming and functional information, refer to the MSC8144 SC3400 DSP Core Reference Manual, available with a signed non-disclosure agreement. Contact your local Freescale dealer or sales representative for more information. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-1...
Page 416: Memory Management Unit (Mmu)
— A burst size of 1 or 4 for the data fetch unit (DFU) and instruction fetch unit (IFU). — Pre-fetch line enable. — System/shared attributes — Global attributes — Write policy for data memory — L2 cache policy data memory MSC8144E Reference Manual, Rev. 3 11-2 Freescale Semiconductor...
Page 417 Precise interrupts allowing handling MMU MATT misses supporting a virtually paged operating system. Core branch target buffer (BTB) that enables manual and automatic BTB maintenance. Platform error detection code (EDC) recovery scheme. Enable/disable EDC exception mechanism. Peripherals error handling. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-3...
Page 418: Instruction Channel (Icache And Ifu)
Global lock allows locking of all cache lines to reduce the cache restoration penalty of a restored task. In this case, the cache does not serve cache misses. MSC8144E Reference Manual, Rev. 3 11-4 Freescale Semiconductor...
Page 419 MMU without invalidating the appropriate cache lines — XP double match. This is an error that occurs when a task-shared access has an address that matches a non-shared cache line. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-5...
Page 420: Data Channel And Write Queue (Dcache)
Supports Pseudo-LRU (PLRU) as the cache Line Replacement Mechanism (LRM). Partial lock allows locking of a subset of cache lines based on ways boundaries, to reduce cache restoration penalty of a restored task. Data can be locked in the cache, thus MSC8144E Reference Manual, Rev. 3 11-6 Freescale Semiconductor...
Page 421 MMU without flushing/invalidating the appropriate cache lines — Xa/Xb double match: This is an error that occurs when a task-shared access has an address that matches a non-shared cache line. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-7...
Page 422: L2 Instruction Cache
Register ICache ICache Fetch Unit Fetch Unit Block Memory Memory Port 2 Port 1 Port 0 CLASS Initiator IQBus3 IQBus2 IQBus0 IQBus1 Core3 Core2 Core1 Core0 Figure 11-1. L2 ICache Block Diagram MSC8144E Reference Manual, Rev. 3 11-8 Freescale Semiconductor...
Page 423 • Watch point event. • Overflow. — Error detection and correction in L2 ICache memory (single-bit detection and correction with no assurance for multi-bit detection. Automatic built-in-self-test (ABIST) of the ICache memory. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-9...
Page 424: Class
L2 ICache is the same model as that used for linking the DSP core subsystems to the MSC8144E peripherals and MBus (see Chapter 4, Chip-Level Arbitration and Switching System (CLASS) for details). There are two CLASS modules in the L2 ICache, referred to as the CLASS initiator and the CLASS target.
Page 425: Icache Modules
11.4.3 Instruction Fetch Unit The instruction fetch unit is active only for L2 ICache cacheable accesses. It requests fetch sets from devices connected to the MBus and drives that data to the L2 ICache memory. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-11...
Page 426: L2 Icache Register Block
L2IC_CEN[DEN] bit (see Section 11.8.11) to enable the cacheable range. Because the default value disables the address range, you must enable the window to enable the cache. The L2 ICache can begin normal operation for cacheable and non-cacheable requests. MSC8144E Reference Manual, Rev. 3 11-12 Freescale Semiconductor...
Page 427: L2 Icache Global Invalidation Command
L2 ICache lines are not replaced. The locking is done in way boundaries. The reduced open boundaries contain 2 or 4 ways. The exact partial lock configuration is programmed via dedicated register. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-13...
Page 428: L2 Icache Line Replacement
B3 = 1 B4 = 0 B4 = 1 B5 = 0 B5 = 1 B6 = 0 B6 = 1 Replace Replace Replace Replace Replace Replace Replace Replace Figure 11-3. PLRU Replacement Algorithm MSC8144E Reference Manual, Rev. 3 11-14 Freescale Semiconductor...
Page 429: Plru Bit Updates
(one line per cycle), and compares the line address, which is a combination of its Tag and Index, to an address range defined in dedicated registers. The sweep operation MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-15...
Page 430: Invalidation Sweep
In such a case, the sweep command is performed on all cache lines. Note that global invalidation is performed in parallel on all cache lines in one cycle, not serially. MSC8144E Reference Manual, Rev. 3 11-16 Freescale Semiconductor...
Page 431: Fetch Operation
Do not clear the Debug mode bit directly by setting the ECR[EX] bit to force the DSP core subsystem into its execution state. Use the following steps to exit the L2 ICache debug mode: MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-17...
Page 432: Initialize/Read And Update State Registers
Read tag array state register: way 0, index 31, ETAG bits (in L2IC_B1) re-load Read tag array state register: way 1, index0, ETAG bits (in L2IC_B1) re-load Read tag array state register: way 1, index1, ETAG bits (in L2IC_B1) re-load MSC8144E Reference Manual, Rev. 3 11-18 Freescale Semiconductor...
Page 433 Read PLRU state register: index 28–index 31, PLRU bits (in L2IC_B1) re-load Read PLRU state register: index 0–index 3, PLRU bits (in L2IC_B2) re-load Read PLRU state register: index 4–index 7, PLRU bits (in L2IC_B2) re-load MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-19...
Page 434 Continue Reading from same address Read Valid state register: way 1, index 31, valid bits (in L2IC_B2) re-load Continue Reading from same address Read Valid state register: way 8, index0, valid bits (in L2IC_B2) re-load MSC8144E Reference Manual, Rev. 3 11-20 Freescale Semiconductor...
Page 435: L2 Icache Array Access During Debug
• Way selection to the DW field in bits 18–16. • Address lsbs to the DBGAD field in bits 13–0. • Access size in bytes to the DABE field in bits 21–20. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-21...
Page 436: M2 Memory
DSP cores. To reduce possible impact of soft error rate (SER) on systems using the MSC8144E, the M2 employs error correction code (ECC). The ECC being deployed adds 7 bits of ECC on each 64 MSC8144E Reference Manual, Rev.
Page 437: M3 Memory
4 × 128-bit to generate a sustained bandwidth of 128-bit at 400 MHz between the M3 memory and the rest of the MSC8144E device. As a DRAM, the memory must be refreshed. The whole refresh operation occurs in parallel to regular accesses and is almost completely hidden from the user.
Page 438: Internal Boot Rom
11.7 Internal Boot ROM The MSC8144E device includes 96 KB of boot ROM accessible from all of the cores. This ROM provides the basic loading programming that allows the device to complete its initialization and load additional configuration and booting from external sources.
Page 439: Programming Model
The following three registers use a base address of 0xFFF2A000. L2 ICache Cacheable Area Start Address (L2IC_CSA), see page 11-34. L2 ICache Cacheable Area End Address (L2IC_CEA), see page 11-35. L2 ICache Cacheable Area Enable (L2IC_CEN), see page 11-36. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-25...
Page 440: L2 Icache Control Register 0 (L2Ic_Cr0)
When programming this field, you must make sure that it is greater than or equal to the sweep start address (L2IC_CR0[SSPA]). — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 11-26 Freescale Semiconductor...
Page 441 Enable Bit is clear. Any attempt to initialize a sweep command is ignored if cache debug mode is enabled. Any attempt to initialize state registers is ignored when cache debug mode is disabled. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-27...
Page 442: L2 Icache Control Register 2 (L2Ic_Cr2)
During debug mode, update mechanisms are disabled and debug registers are accessible. Cache memory is accessible through cache debug registers. An attempt to set this bit while sweep operation is not complete is not allowed. MSC8144E Reference Manual, Rev. 3 11-28 Freescale Semiconductor...
Page 443: L2 Icache Lrm State Register (L2Ic_Lrm)
Reserved. Write to zero for future compatibility. PLRUB2 PLRU Bits 2 Cache line not valid. Holds the state] bits for indexes (4 × i) + 2 (i is an 22–16 Cache line valid. integer). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-29...
Page 444 Cache line not valid. Holds the state] bits for indexes (4 × i) (i is an 6–0 Cache line valid. integer). Table 11-10. PLRU Replacement Way Selection PLRU Bits Way Selected for Replacement MSC8144E Reference Manual, Rev. 3 11-30 Freescale Semiconductor...
Page 445: L2 Icache Tag State Register (L2Ic_Tag)
Indicates whether the whole cache line is valid or Cache line valid. not. — Reserved. Write to zero for future compatibility. 22–18 0x3FFFF 17–0 Indicates directly the status of the debugged TAG according to a dedicated debug counter. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-31...
Page 446: L2 Icache Valid State Register (L2Ic_Valid)
This register is accessible only in L2 ICache debug mode. L2IC_DBG_DATA bit fields. Table 11-13. L2IC_DBG_DATA Bit Descriptions Name Reset Description Settings DDATA Debug Data 31–0 This field contains the read/ write data in debug mode. MSC8144E Reference Manual, Rev. 3 11-32 Freescale Semiconductor...
Page 447: L2 Icache Debug Access Register (L2Ic_Dbg_Acs)
Reserved. Write to zero for future compatibility. Debug Way Way 0. the way number of the accessed data 18–16 Defines Way 1. Way 2. Way 3. Way 4. Way 5. Way 6. Way 7. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-33...
Page 448: L2 Icache Cacheable Area Start Address (L2Ic_Csa)
— Reserved. Write to zero for future compatibility. 31–20 Start Address 19–0 Contains the 20 msbs of the L2 ICache cacheable window start address (bits 31–12). The 12 lsbs are all zeros. MSC8144E Reference Manual, Rev. 3 11-34 Freescale Semiconductor...
Page 449: L2 Icache Cacheable Area End Address (L2Ic_Cea)
Contains the 20 msbs of the L2 ICache cacheable window end address. The 12 lsbs are all zeros. When programming this value, make sure it is greater than or equal to the value stored in L2IC_CSA. If the values are equal, the address window is 4 KB in size. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-35...
Page 450: L2 Icache Cacheable Area Enable (L2Ic_Cen)
Table 11-17. L2IC_CEN Bit Descriptions Name Reset Description Settings — Reserved. Write to zero for future compatibility. 31–1 Cacheable Window Disable/Enable Window disabled (all accesses non-cacheable). Activates/deactivates the cacheable window. Window enabled. MSC8144E Reference Manual, Rev. 3 11-36 Freescale Semiconductor...
Page 451: L2 Icache Programming Limitations
L2 ICache does not support nested sweeps. Avoid it by using a dedicated semaphore and polling the relevant L2 ICache Control Register bit (see Section 11.8.2). ECC is not supported during debug mode and to L2 ICache addresses written during debug. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 11-37...
Page 452 Internal Memory Subsystem MSC8144E Reference Manual, Rev. 3 11-38 Freescale Semiconductor...
Page 453: Ddr Sdram Memory Controller
MDQS[0–4] Signals Management Delay Chain MDQS[0–4] Data from FIFO Data Signals SDRAM MDQ[0–31] MECC[0–7] SDRAM Control Data from Clocks Initiator Clock MCK[0–2] Control MCK[0–2] Figure 12-1. DDR SDRAM Memory Controller Block Diagram MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-1...
Page 454: Architecture
When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct single-bit errors. ECC generation does not add a cycle to the write path. MSC8144E Reference Manual, Rev. 3 12-2 Freescale Semiconductor...
Page 455 Figure 12-3 shows some typical signal connections. 64 M × 1 Byte 512 Mbit ADDR A[12–0] DQ[7–0] Data BA[1–0] BANK ADDR Data MRAS Strobe MCAS Command Write Enable Figure 12-3. Typical DDR SDRAM Interface Signals MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-3...
Page 456: Ddr Sdram Interface Operation
An 8-bit DDR SDRAM device has a signal and eight data signals ( ). A DQ[0–7] 16-bit DDR SDRAM device has two signals associated with specific halves of the 16 data signals ( DQ[0–7] DQ[8–15] MSC8144E Reference Manual, Rev. 3 12-4 Freescale Semiconductor...
Page 457 2. Each MCS[0–1] signal corresponds with a separate physical bank of memory. 3. MCK[0–2] can be apportioned among all memory devices. Complementary bus is not shown. Figure 12-4. Example 64 MB DDR SDRAM Configuration With ECC MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-5...
Page 458: Ddr Sdram Organization
1 GB 512 Mb × 8 16 × 11 × 2 4 Gb 2 GB 4 GB 256 Mb × 16 16 × 10 × 2 4 Gb 512 MB 2 GB MSC8144E Reference Manual, Rev. 3 12-6 Freescale Semiconductor...
Page 459: Ddr Sdram Address Multiplexing
The address at the memory controller signals as the MSB and MA[15–0] MA15 as the LSB. Also, is the auto-precharge bit in DDR1/DDR2 modes for reads and writes, MA10 so the column address can never use MA10 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-7...
Page 460 9 8 7 6 5 4 3 2 1 0 MRAS 12 11 10 9 8 7 6 5 4 3 2 1 0 MCAS 8 7 6 5 4 3 2 1 0 MSC8144E Reference Manual, Rev. 3 12-8 Freescale Semiconductor...
Page 461 9 8 7 6 5 4 3 2 1 0 MRAS 12 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0 MCAS 9 8 7 6 5 4 3 2 1 0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-9...
Page 462: Jedec Standard Ddr Sdram Interface Commands
The amount of data transferred is determined by the data masks and the burst size, which is set to four by the DDR memory controller. MSC8144E Reference Manual, Rev. 3 12-10 Freescale Semiconductor...
Page 463 Column Read with Logical bank select Column auto-precharge Write Logical bank select Column Write with Logical bank select Column auto-precharge Mode register set Opcode Opcode Opcode and mode Auto refresh Self refresh MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-11...
Page 464: Ddr Sdram Clocking And Interface Timing
READ command by the SDRAM and the availability of the first piece of output data. If a READ command is registered at clock edge , and the read latency is clocks, the data is available nominally coincident with clock edge MSC8144E Reference Manual, Rev. 3 12-12 Freescale Semiconductor...
Page 465 System software is responsible at reset for optimally configuring SDRAM timing parameters. The programmable timing parameters apply to both read and write timing configuration. The configuration process must be completed and the DDR SDRAM initialized before attempting any accesses to SDRAM. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-13...
Page 466 Latency = 2 MCAS SDRAM Clock ACTTORW PRECHARGE MRAS MCAS WRREC PRETOACT MA[15–0] A10=0 MDQ[0–31] D0 D1 D2 D3 MDQS MDM[0–3] Figure 12-6. DDR SDRAM Single-Beat (Word) Write Timing: ACTTORW = 3 MSC8144E Reference Manual, Rev. 3 12-14 Freescale Semiconductor...
Page 467: Clock Distribution
DQ[0–7], DQS0, DM0 MCK0, MCK1, MCK0 MCK1 DQ[8–15], DQS1, DM1 DQ[16–23], DQS2, DM2 DQ[24–31], DQS3, DM3 ECC[0–7], DQS4, DM4 MCK2, MCK2 Figure 12-8. DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-15...
Page 468: Ddr Sdram Mode-Set Command Timing
SDRAM clock cycle after the command is launched. The delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0. Figure 12-10 shows the use of the write data delay parameter. MSC8144E Reference Manual, Rev. 3 12-16 Freescale Semiconductor...
Page 469: Ddr Sdram Refresh
Completes all current memory requests. Closes all open pages with a command to each DDR SDRAM bank PRECHARGE ALL with an open page (as indicated by the row open table). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-17...
Page 470: Ddr Sdram Refresh Timing
MCAS MA[15–0] Note: The DDR controller is designed to support up to six banks. MSC8144E uses only two banks The third refresh command is used for devices with more than two banks. Figure 12-11. DDR SDRAM Bank Staggered Auto Refresh Timing MSC8144E Reference Manual, Rev.
Page 471: Ddr Sdram Refresh And Power-Saving Modes
Figure 12-12. Memory Bus Clock COMMAND Figure 12-12. DDR SDRAM Power-Down Mode The entry and exit timing for self-refreshing SDRAMs in Sleep mode is shown in Figure 12-13 and Figure 12-14. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-19...
Page 472 MRAS MCAS MA[15:0] (High Impedance) MDQ[0–31] MDQS Figure 12-13. DDR SDRAM Self-Refresh Entry Timing SDRAM Clock MRAS MCAS MA[15:0] (High Impedance) MDQ[0–31] MDQS 200 cycles Figure 12-14. DDR SDRAM Self-Refresh Exit Timing MSC8144E Reference Manual, Rev. 3 12-20 Freescale Semiconductor...
Page 473: Ddr Memory Controller Clock Stop Mode
DDR memory while in stop mode will not be executed by the controller and the MSC8144E might get stuck. To prevent this stuck condition it is possible to disable the DDR window within the CLASS by deasserting REGISTER[bit] prior to requesting the stop mode.
Page 474: Page Mode And Logical Bank Retention
DDR SDRAM Memory Controller Note: For MSC8144E the DDR controller will not perform wrapped accesses. Accesses that their start address is not aligned to 16 or 8 byte (according to the actual mode) and crosses the alignment boundary will be split into two accesses toward the memory. For...
Page 475 • • • • • • • • • • • • • • • Table 12-11. DDR SDRAM ECC Syndrome Encoding (Check Bits) Syndrome Bit Check • • • • • MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-23...
Page 476: Error Management
If the DDR memory controller is not using sample points, then a dummy transaction is issued to DDR SDRAM with the first enabled chip select. Table 12-12 describes the errors. MSC8144E Reference Manual, Rev. 3 12-24 Freescale Semiconductor...
Page 477: Set-Up And Initialization
DDR device connected to the MSC8144. For DDR1 devices the DDR_GCR[DDR_VSEL] = 0 (reset value), for DDR2 devices the DDR_GCR[DDR_VSEL] = 1 Programming the correct value is essential for the correct MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-25...
Page 478 ECC Enable (ECC_EN) page 12-43 (DDR_SDRAM_CFG) SDRAM Type (SDRAM_Type) Dynamic Power Management Mode (DYN_PWR) 32-Bit Bus Enable (32_BE) Non-Current Auto Precharge (NCAP) 2T Timing Enable (2T_EN) Half-Strength Drive Enable (HSE) Bypass Initialization (BI) MSC8144E Reference Manual, Rev. 3 12-26 Freescale Semiconductor...
Page 479: Programming Differences Between Memory Types
Table 12-14. Programming Differences Between Memory Types Parameter Description Differences Page DDR1 Chip Select x Auto Can be used to place chip select x into auto Table 12-17 on AP_x_EN Precharge Enable precharge mode. page 12-33 DDR2 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-27...
Page 480 Table 12-21 on Configure to CAS latency – 1 cycle. For WR_LAT Write Latency page 12-40 DDR2 example, if the CAS latency if 5 cycles, then configure this field to 100 (4 cycles). MSC8144E Reference Manual, Rev. 3 12-28 Freescale Semiconductor...
Page 481: Ddr Sdram Initialization Sequence
DDR memory controller conducts an automatic initialization sequence to the memory, which follows the memory specifications. If the bypass initialization mode is used, software can initialize the memory through the DDR_SDRAM_MD_CNTL register. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-29...
Page 482: Memory Controller Programming Model
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG), page 12-42. DDR SDRAM Control Configuration 2 Register (DDR_SDRAM_CFG_2), page 12-44. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE), page 12-46. DDR SDRAM Mode Configuration 2 Register (DDR_SDRAM_MODE_2), page 12-47. MSC8144E Reference Manual, Rev. 3 12-30 Freescale Semiconductor...
Page 483 MDIC Output Enable Control Register (MDIC_OE_CONT), page 12-65. DDR SDRAM Termination, OCD, and ODT Control Register (TERM_OCD_ODT_CONT), page 12-66. Clock Ratio Control Register (CLK_RATIO_CONT), page 12-67. Note: The DDR controller registers use a base address of: 0xFFF20000. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-31...
Page 484: Chip-Select Bounds (Csx_Bnds)
Reserved. Cleared to zero for future compatibility. 15–9 Ending Address 8–0 Specifies the ending address for chip select (bank) x. This value is compared against the 8 MSBs of the 32-bit address. See the previous note. MSC8144E Reference Manual, Rev. 3 12-32 Freescale Semiconductor...
Page 485: Chip-Select X Configuration Register (Csx_Config)
Assert ODT only during reads to to be enabled. ODT should be used only with DDR2 other chip selects. memories. Reserved. Assert ODT for all reads. 101–111 Reserved. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-33...
Page 486: Ddr Sdram Extended Refresh Recovery Register (Timing_Cfg_3)
Table 12-5 and Table 12-6 for details. 11 column bits. 100–111 Reserved. 12.7.3 DDR SDRAM Extended Refresh Recovery Register (TIMING_CFG_3) TIMING_CFG_3 DDR SDRAM Extended Refresh Recovery Register Offset 0x0100 — REFR Type Reset — Type Reset MSC8144E Reference Manual, Rev. 3 12-34 Freescale Semiconductor...
Page 487: Ddr Sdram Timing Configuration Register 0 (Timing_Cfg_0)
CL – WL + BL/2 + 2. CL is the latency rounded up to the next integer, WL is the programmed write latency, and BL is the burst length. (BL = 4 for all accesses) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-35...
Page 488 2 clock cycles. The default is one clock cycle. 3 clock cycles. 4 clock cycles. 5 clock cycles. 6 clock cycles. 7 clock cycles. — Reserved. Write to zero for future compatibility. 15–12 MSC8144E Reference Manual, Rev. 3 12-36 Freescale Semiconductor...
Page 489 1000 8 clock cycles. 1001 9 clock cycles. 1010 10 clock cycles. 1011 11 clock cycles. 1100 12 clock cycles. 1101 13 clock cycles. 1110 14 clock cycles. 1111 15 clock cycles. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-37...
Page 490: Ddr Sdram Timing Configuration Register 1 (Timing_Cfg_1)
AC specifications of the SDRAM. 3 clock cycles. This field must be programmed for proper operation of the DDR Controller. 4 clock cycles. 5 clock cycles. 6 clock cycles. 7 clock cycles. MSC8144E Reference Manual, Rev. 3 12-38 Freescale Semiconductor...
Page 491 This field must be programmed for proper operation of the DDR 4 clock cycles. Controller. 5 clock cycles. 6 clock cycles. 7 clock cycles. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-39...
Page 492: Ddr Sdram Timing Configuration Register 2 (Timing_Cfg_2)
The additive latency must be set to a value less than 1 clock cycle. TIMING_CFG_1[ACTTORW]. 2 clock cycles. This timing parameters applies to DDR2 only 3 clock cycles. 4 clock cycles. 5 clock cycles. 110–111 Reserved. MSC8144E Reference Manual, Rev. 3 12-40 Freescale Semiconductor...
Page 493 2 clock cycles. For DDR1 must be set to 010. 3 clock cycles. This field must be programmed for proper operation of the DDR Controller. 4 clock cycles. 101–111 Reserved MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-41...
Page 494: Ddr Sdram Control Configuration Register (Ddr_Sdram_Cfg)
Type Reset DDR_SDRAM_CFG enables the interface logic and specifies certain operating features such as self refreshing, error checking and correcting and dynamic power management. The default value is 0b010, designating DDR1 SDRAM. MSC8144E Reference Manual, Rev. 3 12-42 Freescale Semiconductor...
Page 495 DRAM command/address are held for two full clock cycles. on the DRAM bus for every DRAM transaction. However, the chip select is held only for the second cycle. — Reserved. Write to zero for future compatibility. 14–4 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-43...
Page 496: Ddr Sdram Control Configuration Register 2 (Ddr_Sdram_Cfg_2)
DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2) DDR_SDRAM_CFG_2 DDR SDRAM Control Configuration Register 2 Offset 0x0114 DLL_ FRC_ — RST_ — DQS_CFG — ODT_CFG — Type Reset NUM_PR — D_INIT — Type Reset MSC8144E Reference Manual, Rev. 3 12-44 Freescale Semiconductor...
Page 497 SDRAMs cannot use more than three posted 1000 8 refreshes at a time. refreshes because the required refresh interval can 1001–1111Reserved. exceed the maximum constraint for t — Reserved. Write to zero for future compatibility. 11–5 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-45...
Page 498: Ddr Sdram Mode Configuration Register (Ddr_Sdram_Mode)
SDRAM mode register value must be stored at MODCFG bit 15. Because the memory controller forces SDMODE[8] to certain values depending upon the state of the initialization sequence (for resetting the SDRAM DLL), the memory controller ignores the corresponding bits of this field. MSC8144E Reference Manual, Rev. 3 12-46 Freescale Semiconductor...
Page 499 DDR SDRAM Mode Control Register Offset 0x0120 MDEN — CSSEL — MDSEL SETR SETPRE CKECTL — Type Reset Type Reset DDR_SDRAM_MD_CNTL allows software to force mode/extended mode register set commands to DRAM. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-47...
Page 500 1 A precharge all command is ready sets this bit, and hardware clears it when the command is to issue. issued. Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; they cannot be set at the same time MSC8144E Reference Manual, Rev. 3 12-48 Freescale Semiconductor...
Page 501 SDRAM CFG2 {NUM_PR] some number of rows are refreshed in each DDR SDRAM physical bank during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface clock frequency. Refreshes are not issued when REFINT is cleared to all 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-49...
Page 502: Ddr Sdram Data Initialization Register (Ddr_Data_Init)
Specifies the initialization value for the DRAM if DDR_SDRAM_CFG_2[D_INIT] is set. 12.7.14 DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL) DDR_SDRAM_CLK_CNTL DDR SDRAM Clock Offset 0x0130 Control Configuration Register — CLK_ADJUST — Type Reset — Type Reset MSC8144E Reference Manual, Rev. 3 12-50 Freescale Semiconductor...
Page 503: Ddr Sdram Initialization Address Register (Ddr_Init_Address)
DDR_SDRAM_CFG_2[D_INIT] bit. However, if is asserted after the DRAM Reset enters Self-Refresh mode, memory is not initialized. Therefore this address should be written to avoid possible ECC errors when this address is accessed later. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-51...
Page 504: Ddr Sdram Initialization Address Enable Register (Ddr_Init_En)
1 Use the initialization address programmed in DDR_INIT_ADDRESS. — Reserved. Write to zero for future compatibility. 30–0 MSC8144E Reference Manual, Rev. 3 12-52 Freescale Semiconductor...
Page 505: Ddr Sdram Ip Block Revision 1 Register (Ddr_Ip_Rev1)(
DDR_IP_REV2 provides read-only fields with the IP block integration and configuration options. Table 12-33. DDR_IP_REV2 Bit Descriptions Reset Description — Reserved. Write to zero for future compatibility. 31–24 IPINT IP Block Integration Options 23–16 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-53...
Page 506 Tests ECC by forcing errors on the high bytes of the data path. Setting a bit causes the corresponding data path bit to be inverted during memory bus writes. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 12-54 Freescale Semiconductor...
Page 507 12.7.21 DDR SDRAM Memory Data Path Error Injection Mask ECC Register (DDR_ERR_INJECT) DDR_ERR_INJECT DDR SDRAM Memory Data Path Offset 0x0E08 Error Injection Mask ECC Register — Type Reset — EIEN EEIM Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-55...
Page 508 Reserved. Write to zero for future compatibility. 23–16 CDHlSB Error Capture High Data Path 15–8 Captures bits 8–15 of the data path when errors are detected. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 12-56 Freescale Semiconductor...
Page 509 Reserved. Write to zero for future compatibility. 7–0 12.7.24 DDR SDRAM Memory Data Path Read Capture ECC Register (CAPTURE_ECC) CAPTURE_ECC DDR SDRAM Memory Data Path Read Offset 0x0E28 Capture ECC Register — Type Reset — Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-57...
Page 510: Ddr Sdram Memory Error Detect Register (Err_Detect)
Reserved. Write to zero for future compatibility. 6–4 Multiple-Bit Error Multiple-bit error not detected. Indicates whether a multiple-bit error was Multiple-bit error detected. detected. This bit is cleared by software writing a 1 to it. MSC8144E Reference Manual, Rev. 3 12-58 Freescale Semiconductor...
Page 511: Ddr Sdram Memory Error Disable Register (Err_Disable)
CCFG[ECC_EN] is set. They are reported if ERR_INT_EN[MBEE] is set. SBED Single-Bit ECC Error Disable Single-bit ECC errors detection is Enables/disables single-bit ECC errors detection. enabled. Single-bit ECC errors detection is disabled. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-59...
Page 512: Ddr Sdram Memory Error Interrupt Enable Register (Err_Int_En)
Reserved. Write to zero for future compatibility. MSEE Memory Select Error Interrupt Enable Memory select errors do not generate Specifies whether memory select errors generate interrupts. interrupts. Memory select errors generate interrupts. MSC8144E Reference Manual, Rev. 3 12-60 Freescale Semiconductor...
Page 513 Specifies the access type that generates the error. 01 Write. 10 Read. 11 Read-modify-write. — Reserved. Write to zero for future compatibility. 11–1 Valid Set as soon as valid information is captured in the error capture registers. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-61...
Page 514 12.7.30 DDR SDRAM Single-Bit ECC Memory Error Management Register (ERR_SBE) ERR_SBE DDR SDRAM Single-Bit ECC Memory Error Offset 0x0E58 Management Register — SBET Type Reset — SBEC Type Reset MSC8144E Reference Manual, Rev. 3 12-62 Freescale Semiconductor...
Page 515: Ddr Sdram Ddr Status (Ddr_Stop_Status)
Reset value 0xC represents the nominal impedance 1100 Driver P-Impedance Status 11–8 Results of driver calibration. Reset value 0xC represents the nominal impedance — Reserved. Write to zero for future compatibility. 7–2 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-63...
Page 516: Dddr Sdram Power Control Register (Ddr_Pwr)
This bit affects only the software method for entering self refresh. STOP Stop Request to Memory Controller No stop request. Specifies whether a stop request is sent to the Stop request to memory controller. memory controller. MSC8144E Reference Manual, Rev. 3 12-64 Freescale Semiconductor...
Page 517 Forces the output enable to be set only if TERM_OCD_ODT_CO TERM_OCD_ODT_CONT[DCOV] is also set. NT[DCOV] is set, force MDIC0_OE to disable 1 - if TERM_OCD_ODT_CO NT[DCOV] is set, force MDIC0_OE to enable MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-65...
Page 518 75 ohm termination, and a value of 1 indicates 150 ohm termination. P Channel Impedance 7–4 Value for the p-impedance if jdcp_drvr_comp_override is asserted. N Channel Impedance 3–0 Value for the n-impedance if jdcp_drvr_comp_override is asserted. MSC8144E Reference Manual, Rev. 3 12-66 Freescale Semiconductor...
Page 519: Ddr Sdram Clock Ratio Control Register (Clk_Ratio_Cont)
CLASS128 frequency. memory controller clock. CLASS128 clock frequency is higher than memory controller clock frequency. Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 12-67...
Page 520 DDR SDRAM Memory Controller MSC8144E Reference Manual, Rev. 3 12-68 Freescale Semiconductor...
Page 521: Interrupt Handling
— Provides a core-to-core signaling mechanism by virtual interrupt generation. Allows for the enabling/disabling of each interrupt source per core. The MSC8144E supports both internal and external interrupt sources as well as allowing for the generation of an interrupt to external devices.
Page 522: Global Interrupt Controller (Gic)
The core that services the interrupt may clear this status bit by writing a value of one to it, or it may ignore this bit and work locally. MSC8144E Reference Manual, Rev. 3 13-2...
Page 523: Virtual Nmi Generation
General Configuration Block The general configuration block performs services for rare and debug interrupts generated throughout the MSC8144E before they reach the SC3400 EPICs. These services include: Generating ORed interrupt signals towards the SC3400 cores (see Section 13.2.1). Providing an interrupt enable bit for each interrupt source for each SC3400 core (see Section 13.5.2, General Interrupt Configuration, on page 13-15).
Page 524: External Interrupts
Interrupt Handling 13.2.2 External Interrupts The MSC8144E allows a number of external interrupt inputs to be multiplexed with the GPIO signals to enable external devices to interrupt the cores (see Chapter 23, GPIO). There are also dedicated external interrupt pins.
Page 525: Interrupt Handling
General Configuration Block 13.2.3 Interrupt Handling The MSC8144E interrupts sources can be grouped in to four basic types: Interrupts that represent a single interrupt source and are routed directly to the cores (for example, the TDM0 Rx first threshold interrupt).
Page 526: Interrupt Mapping
The interrupts can have an assigned priority from 1(lowest) to 31 (highest) as well as non-maskable (priority 32). The MSC8144 SC3400 DSP core subsystem reserves the first 34 interrupt sources for internal use, leaving 222 available interrupt sources. The MSC8144E does not implement all of these possible sources.
Page 527 Interrupt Mapping Table 13-4. MSC8144E Interrupt Table (Continued) Interrupt Description Level Edge index TDM 6 Tx first threshold TDM 6 Tx second threshold TDM 7 Rx first threshold TDM 7 Rx second threshold TDM 7 Tx first threshold TDM 7 Tx second threshold...
Page 528 Interrupt Handling Table 13-4. MSC8144E Interrupt Table (Continued) Interrupt Description Level Edge index Ethernet 2 Rx 4 — Ethernet 2 Rx 5 — Ethernet 2 Rx 6 — Ethernet 2 Rx 7 — Ethernet 2 Tx 0 — Ethernet 2 Tx 1 —...
Page 529 Interrupt Mapping Table 13-4. MSC8144E Interrupt Table (Continued) Interrupt Description Level Edge index DMA channel 10 EOB — DMA channel 11 EOB — DMA channel 12 EOB — DMA channel 13 EOB — DMA channel 14 EOB — DMA channel 15 EOB —...
Page 530 Interrupt Handling Table 13-4. MSC8144E Interrupt Table (Continued) Interrupt Description Level Edge index Virtual Interrupt 10 — Virtual Interrupt 11 — Virtual Interrupt 12 — Virtual Interrupt 13 — Virtual Interrupt 14 — Virtual Interrupt 15 — Virtual Non Maskable Interrupt 0 —...
Page 531: Restrictions
Restrictions Table 13-4. MSC8144E Interrupt Table (Continued) Interrupt Description Level Edge index OCN DMA Channel 0 Interrupt — Channel 1 Interrupt — Channel 2 Interrupt — Channel 3 Interrupt — General Hardware Interrupt — 13.4 Restrictions Some interrupts can cause the core to deadlock. These interrupts can occur when the core issues a single read towards a peripheral and the read triggers an interrupt.
Page 532 L2 ICache and it is a hit, PM the PM that counts hit events in the counter is set to report a single L2 L2 ICache to 2 or more. ICache hit access. MSC8144E Reference Manual, Rev. 3 13-12 Freescale Semiconductor...
Page 533: Programming Model
Programming Model 13.5 Programming Model The MSC8144E interrupt program model includes configuration of the global interrupt controller and the general configuration block interrupt registers. Note: See the MSC8144 SC3400 DSP Core Subsystem Reference Manual for configuration and programming of the EPIC registers.
Page 534: Virtual Interrupt Status Register (Visr)
Table 13-7. VNMIGR Bit Descriptions Name Description — Reserved. Write to zero for future compatibility. 31–10 VNMINUM Virtual Non Maskable Interrupt Number 9–8 Asserts the corresponding VNMI. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 13-14 Freescale Semiconductor...
Page 535: General Interrupt Configuration
Table 13-8. GIR1 Bit Descriptions Name Description Settings — Reserved. Write to zero for future compatibility. 31–12 VNMI_3 Virtual NMI 3 Interrupt not asserted Asserted when VNMI_3 is activated Interrupt asserted MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 13-15...
Page 536: General Interrupt Enable Register 1 For Cores 0–3 (Gier1_[0–3])
‘General Interrupt Enable Register 1 for Cores 0–3 Offset 0x44 GIER1_1 Offset 0x48 GIER1_2 Offset 0x4C GIER1_3 Offset 0x50 — Type Reset — Type Reset — Type Reset — M2_3_ECC_EN M2_2_ECC_EN M2_1_ECC_EN M2_0_ECC_EN Type Reset MSC8144E Reference Manual, Rev. 3 13-16 Freescale Semiconductor...
Page 537: General Interrupt Register 2 (Gir2)
Type Reset GIR2 includes interrupt status of some events within MSC8144E that are rare. Those bits are not sticky but only sample the events. The GIR2 register is reset on a hard reset event. All bits are cleared on reset Table 13-10.
Page 538 Interrupt asserted TDM4_TERR TDM4 Transmit Error Interrupt Interrupt not asserted Reflects TDM4 Transmit error interrupt Interrupt asserted TDM4_RERR TDM4 Receive Error Interrupt Interrupt not asserted Reflects TDM4 Receive error interrupt Interrupt asserted MSC8144E Reference Manual, Rev. 3 13-18 Freescale Semiconductor...
Page 539: General Interrupt Enable Register 2 For Cores 0–3 (Gier2_[0–3])
Type Reset PCI_ERR_EN DDR_ERR_EN DMA_ERR_EN — CE_IECC_EN CE_DECC_EN TDM_P1ECC_EN TDM_P0ECC_EN Type Reset TDM7_TERR_EN TDM7_RERR_EN TDM6_TERR_EN TDM6_RERR_EN TDM5_TERR_EN TDM5_RERR_EN TDM4_TERR_EN TDM4_RERR_EN Type Reset TDM3_TERR_EN TDM3_RERR_EN TDM2_TERR_EN TDM2_RERR_EN TDM1_TERR_EN TDM1_RERR_EN TDM0_TERR_EN TDM0_RERR_EN Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 13-19...
Page 540 Interrupt enabled TDM6_TERR_EN TDM6 Transmit Error Interrupt Enable/Disable Interrupt disabled Interrupt enabled TDM6_RERR_EN TDM6 Receive Error Interrupt Enable/Disable Interrupt disabled Interrupt enabled TDM5_TERR_EN TDM5 Transmit Error Interrupt Enable/Disable Interrupt disabled Interrupt enabled MSC8144E Reference Manual, Rev. 3 13-20 Freescale Semiconductor...
Page 541: General Interrupt Register 3 (Gir3)
— Type Reset — — — — — — — — Type Reset — — — — L2ICS_WP L2ICS_OV L2ICM_WP Type Reset L2ICM_OV CLS2_WP CLS2_OV CLS1_ERR CLS1_WP CLS1_OV CLS0_WP CLS0_OV Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 13-21...
Page 542 Interrupt Handling GIR3 includes interrupt status of some debug/profiling events within MSC8144E. Those bits are not sticky but only sample the events. The GIR3 register is reset by a hard reset event. All bits are cleared on reset Table 13-12. GIR2 Bit Descriptions...
Page 543: General Interrupt Enable Register 3 For Cores 0–3 (Gier3_[0–3])
Reset GIER3_[0–3] include interrupt enable bits for cores 0–3 for debug/profiling events within MSC8144E. GIER3_[0–3] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this register can be performed only in supervisor mode Table 13-13.
Page 544 CLASS1 Watchpoint Interrupt Enable Interrupt disabled Interrupt enabled CLS1_OV_EN CLASS1 Overrun Interrupt Enable Interrupt disabled Interrupt enabled CLS0_WP_EN CLASS0 Watchpoint Interrupt Enable Interrupt disabled Interrupt enabled CLS0_OV_EN CLASS0 Overrun Interrupt Enable Interrupt disabled Interrupt enabled MSC8144E Reference Manual, Rev. 3 13-24 Freescale Semiconductor...
Page 545 Figure 14-1 shows the VCOP block diagram. Debug and MBus Profiling Interface FIFO PRAM Interface DMA Logic Register File Channel Logic and Arbitration Interrupt Bus Internal Bus Peripheral Requests Figure 14-1. DMA Controller Block Diagram MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-1...
Page 546: Operating Modes
Updates the multi-dimension parameters (multi dimension-buffers) The sections that follow provide examples of several types of buffers. The BD_ATTR fields listed for each example are only those that do not have zero values. MSC8144E Reference Manual, Rev. 3 14-2 Freescale Semiconductor...
Page 547: One-Dimensional Simple Buffer
Generate interrupt when buffer ends. CONT Non-continuous mode: the buffer closes when the size reaches zero. Increment BD_ADDR when the size reaches zero. BTSZ Maximum transfer size is one burst of 64 bytes. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-3...
Page 548: One-Dimensional Cyclic Buffer
Continuous mode: the buffer is not closed when the size reaches zero. Reinitialize BD_ADDR to original value when the size reaches zero. BTSZ Maximum transfer size is one burst of 64 bytes. MSC8144E Reference Manual, Rev. 3 14-4 Freescale Semiconductor...
Page 549: One-Dimensional Chained Buffer
Buffer base size of cyclic buffer. BD_ATTR Generate interrupt when buffer ends. CONT Non-continuous mode. Close the buffer when size reaches zero. Non-cyclic mode. BTSZ Maximum transfer size is one burst of 64 bytes. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-5...
Page 550: One-Dimensional Incremental Buffer
Generate interrupt when buffer ends. CONT Continuous mode. Do not close the buffer when size reaches zero. Increment BD_ADDRESS when size reaches zero. Next request calls buffer 0 when size reaches zero. MSC8144E Reference Manual, Rev. 3 14-6 Freescale Semiconductor...
Page 551: One-Dimensional Complex Buffers With Dual Cyclic Buffers
Continuous mode. Do not shut down the channel when size reaches zero Reinitialize BD_ADDRESS to original value when size reaches zero When size reaches zero, the next request calls buffer 0 BTSZ Maximum transfer size is one burst of 64 bytes MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-7...
Page 552: Two-Dimensional Simple Buffer
0x40 bytes. The second dimension is composed of 0x80 lines of 0x40 bytes each. The offset between each 0x40 byte transaction is 0x1c0. The channel closes when the transfer completes after 0x80 iterations, and an interrupt is generated. Burst transactions are used on the bus. MSC8144E Reference Manual, Rev. 3 14-8 Freescale Semiconductor...
Page 553 Third dimension iterations left. M3D_BCOUNT Third dimension base number of iterations. M3D_OFFSET Third dimension offset between two consecutive iterations. BD_MD_4D M4D_COUNT Fourth dimension iterations left. M4D_OFFSET Fourth dimension offset between two consecutive iterations. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-9...
Page 554: Three-Dimensional Simple Buffer
The MxD_OFFSET is written in two’s complement. The parameters of the fourth dimension must be cleared to zero. Figure 14-8 shows a three-dimensional simple buffer. 0xF3C0 0x103FF 0x8fb0 0x1040 0x1090 0x11b0 0x8f70 0x1000 0x10400 0xF5000 Interrupt 0xF5040 Figure 14-8. Three-Dimensional Simple Buffer MSC8144E Reference Manual, Rev. 3 14-10 Freescale Semiconductor...
Page 555: Four-Dimensional Simple Buffer
All MxD_COUNT must be set to their corresponding dimension parameter. All MxD_OFFSET must be set to the next address offset for the corresponding dimension loop. The MxD_OFFSET is written in two’s complement. Figure 14-9 shows an example four-dimensional simple buffer. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-11...
Page 556 –0xF3FB0 (0x1090 – 0xF5040). The channel closes when the transfer completes after 0x80 iterations of the three-dimensional buffer, and an interrupt is generated. Burst transactions are used on the bus. MSC8144E Reference Manual, Rev. 3 14-12 Freescale Semiconductor...
Page 557: Multi-Dimensional Chained Buffer
(simple, cyclic, or incremental). The chained multi-dimensional buffers can be of any dimension. Figure 14-10 shows a three-dimensional buffer chained to a four-dimensional simple buffer. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-13...
Page 558 DMA logic masks requests until data is out of the source or in the destination. This operation prevents out-of-sequence transactions at the ports. Table 14-9 shows the channel parameter values associated with a three-dimensional chained buffer (BD8) and a four-dimensional simple buffer (BD10). MSC8144E Reference Manual, Rev. 3 14-14 Freescale Semiconductor...
Page 559 0x100 Third dimension base number of iterations. M3D_OFFSET –0xF3FB0 Third dimension offset between two consecutive iterations. BD_MD_4D M4D_COUNT 0x80 Fourth dimension iterations left. M4D_OFFSET 0x24050 Fourth dimension offset between two consecutive iterations. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-15...
Page 560: Two-Dimensional Cyclic Buffer
0x1000. The first dimension is a line of 0x40 bytes. The second dimension is a 0x80 lines of 0x40 bytes each. The offset between each 0x40 bytes transaction is 0x1C0. The base address is restored when the transfer is complete after 0x80 iterations. MSC8144E Reference Manual, Rev. 3 14-16 Freescale Semiconductor...
Page 561: Three-Dimensional Cyclic Buffer
MxD_OFFSET is written in two’s complement. The counters of the fourth dimensions must be cleared to zero. Figure 14-12 shows an example three-dimensional cyclic buffer. 0xF3C0 0x1040 0x1090 0x11b0 0x8FB0 0x103FF 0x8F70 0x1000 0x10400 0xF5000 0xFCFB0 0xF5040 Interrupt Figure 14-12. Three-Dimensional Cyclic Buffer MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-17...
Page 562 Third dimension base number of iterations. M3D_OFFSET –0xF3FB0 Third dimension offset between two consecutive iterations of two dimension buffers. BD_MD_4D M4D_COUNT Fourth dimension iterations left. M4D_OFFSET –0xFBFB0 Fourth dimension offset between two consecutive iterations. MSC8144E Reference Manual, Rev. 3 14-18 Freescale Semiconductor...
Page 563: Arbitration Types
Table 14-12. Round-Robin Arbitration Example Channel Number Channel Request Clock n Priority Clock n+1 Priority Deasserted 0 (Highest) 0 (Highest) Deasserted Asserted Channel 3 win 31 (Lowest) Asserted Asserted Deasserted Deasserted Deasserted 7 (Lowest) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-19...
Page 564: Edf Arbitration
Table 14-14. Example of Channel Priority Sorting Current Time to Priority Priority Priority Priority Channel Threshold Priority (n) Count Deadline Group (n+1) (n+2) (n+3) 0 (winner) 0 (winner) 0 (winner) 0 (winner) MSC8144E Reference Manual, Rev. 3 14-20 Freescale Semiconductor...
Page 565: Issuing Interrupts
Most of the maskable interrupts are issued to request service or indicate that a transfer is available. The exception is EDF threshold violation error interrupt. This interrupt can be masked for each counter. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-21...
Page 566: Nonmaskable Interrupts
Channel Profiled (DEST) bits of the DMA Local Profiling Configuration Register (DMALPCR) (see Table 14-26, DMALPCR Field Descriptions, on page 14-39). These bits provide the following indications: DMA channel active. Arbitration winner. End of buffer for a DMA channel. Bus request. Consecutive grant. MSC8144E Reference Manual, Rev. 3 14-22 Freescale Semiconductor...
Page 567: Dma Programming Model
— DMA Channel Freeze Status Register (DMACHFSTR), page 14-41 DMA Channel Buffer Descriptors — Buffer Attributes (BD_ATTR), page 14-44 — Multi-Dimensional Buffer Attributes (BD_MD_ATTR), page 14-47 Note: The DMA controller registers use a base address of: 0xFFF10000. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-23...
Page 568: Dma Buffer Descriptor Base Registers X (Dmabdbrx)
0111 Destination table offset is 0x800. 1000 Destination table offset is 0x1000. 1001 Destination table offset is 0x2000. 1010 Destination table offset is 0x3000. 1011 Destination table offset is 0x4000. 11xx Reserved. MSC8144E Reference Manual, Rev. 3 14-24 Freescale Semiconductor...
Page 569: Dma Controller Channel Configuration Registers X (Dmachcrx)
The source can be either one-dimensional or Source is multi-dimensional. multi-dimensional. Written by: User DMDC Destination Multi-Dimensional Channel Destination is one-dimensional. The destination can be either one-dimensional or multi- Destination is dimensional multi-dimensional. Written by: User MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-25...
Page 570 The maximum number of one-dimensional BDs per destination is 1024. The maximum number of multi-dimensional BDs per destination is 512. For details on BD address calculation, see Section 14.6.21. Written by: User, DMA controller MSC8144E Reference Manual, Rev. 3 14-26 Freescale Semiconductor...
Page 571: Dma Controller Global Configuration Register (Dmagcr)
Enables the DMA arbitration type. The DMA Enable EDF arbitration. arbitration type is defined in the DMAGCR. See Section 14.3, Arbitration Types, on page 14-19 for details on arbitration. Written by: User MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-27...
Page 572: Dma Channel Enable Register (Dmacher)
CHCRx[ACTV] are all set until the pending channel transactions are closed. When all transactions are closed, the DMA logic resets the DMACHER[ENx] and DMACHCRx[ACTV] bits. After the channel is disabled, you must poll DMACHASTR to acknowledge that the channel MSC8144E Reference Manual, Rev. 3 14-28 Freescale Semiconductor...
Page 573: Dma Channel Freeze Register (Dmachfr)
When the DMA channel becomes frozen, data may be left in the FIFO. 14.6.6 DMA Channel Defrost Register (DMACHDFR). DMACHDFR DMA Channel Defrost Register Offset 0x224 D15 S15 D14 Type Reset Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-29...
Page 574: Dma Time-To-Dead Line Registers X (Dmaedftdlx)
The threshold defines the value of the counter when the DMA task is due. The maximum threshold value is 0xff and the minimum is 2. Note: The DMA logic sets the priority of the channels according to counters threshold value. MSC8144E Reference Manual, Rev. 3 14-30 Freescale Semiconductor...
Page 575: Dma Edf Control Register (Dmaedfctrl)
Divide the clock source (selected by CLK_SRC) for the EDF counters. The DMAEDFTDLx clock frequency is EDF clock (selected by CLK_SRC) divided by CLK_DIV. The maximum CLK_DIV value is 0xFFFF and the minimum is 1. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-31...
Page 576: Dma Edf Mask Register (Dmaedfmr)
Setting the bit enables generation of the respective interrupt request. Interrupt enabled. 14.6.10 DMA EDF Mask Update Register (DMAEDFMUR) DMAEDFMUR DMA EDF Mask Update Register Offset 0x340 MASK_CH3 MASK_CH2 Type Reset: MASK_CH1 MASK_CH0 Reset: MSC8144E Reference Manual, Rev. 3 14-32 Freescale Semiconductor...
Page 577 Stores the new value of DMAEDFMR[MASK_CH0]. Masked. User Enable Mask/Unmask Updating Update occurred. When set, updates DMAEDFMR[MASK_CH0 Perform update. according to NM3. When DMAEDFMR[MASK_CH0] is updated, the DMA controller clears this bit. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-33...
Page 578: Dma Edf Status Register (Dmaedfstr)
If set, each Dx bit enables the generation of interrupt request signal on the corresponding interrupt line. DMAMR is cleared at reset and you can enable a channel interrupt request by setting the appropriate Dx bit. MSC8144E Reference Manual, Rev. 3 14-34 Freescale Semiconductor...
Page 579: Dma Mask Update Register (Dmamur)
NM2. Then the DMA controller clears this bit. Written by: User, DMA controller MASKCH1 Channel Number 00000–01111: Channel number. 15–11 The channel number to which DMAMR should be 1xxxx: Reserved changed. Written by: User MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-35...
Page 580: Dma Status Register (Dmastr)
BD_ATTR[SST] is set or it is the last buffer. A bit is cleared by writing a value of one to it. Writing zero does not affect a bit value. Several bits can be cleared at one time. MSC8144E Reference Manual, Rev. 3 14-36 Freescale Semiconductor...
Page 581: Dma Error Register (Dmaerr)
Reserved. Write to zero for future compatibility. PBCH First Port 1 Channel to Cause Bus Error 000000–001111: channel number. 22–17 Indicates which channel caused the first error on 01xxxx Reserved bus interface port B. 10xxxx: Reserved MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-37...
Page 582 Indicates by which channel the last parity error was 10xxxx Reserved. caused. PRTYD Parity Error Destination Source transaction error. Indicates whether the first parity error was caused Destination transaction error. by a channel source or destination. MSC8144E Reference Manual, Rev. 3 14-38 Freescale Semiconductor...
Page 583: Dma Debug Event Status Register (Dmadesr)
TYPE RESET — CHAPRO DEST TYPE RESET DMALPCR selects the channel for system profiling. Table 14-26. DMALPCR Field Descriptions Bits Reset Description Settings — Reserved. Write to zero for future compatibility. 31–7 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-39...
Page 584: Dma Round-Robin Priority Group Update Register (Dmarrpgur)
The new value of RRPG to be written to the corresponding CHCR of the channel. Lowest priority. Reserved. Enable RRPG Update Enables the RRPG update. Then the DMA controller clears this bit MSC8144E Reference Manual, Rev. 3 14-40 Freescale Semiconductor...
Page 585: Dma Channel Active Status Register (Dmachastr)
Each bit in the DMACHFSTR corresponds to the freeze status of the associated channel. If set, a bit associated with a channel indicates that the channel is still frozen. Note: The corresponding bits are cleared when a channel is activated. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-41...
Page 586: Dma Channel Buffer Descriptors
MBus interface 0. Figure 14-14 shows the structure of one-dimensional BD, which is a 128-bit entry. BD_ADDR BD_SIZE BD_ATTR BD_BSIZE 32 Bits 32 Bits 32 Bits 32 Bits Figure 14-14. DMA Channel BD One-Dimensional Line MSC8144E Reference Manual, Rev. 3 14-42 Freescale Semiconductor...
Page 587 BDs and multi-dimensional BDs are chained only to multi-dimensional BDs. The types of source and destination BDs are defined in the DMACHCR (see page 14-25). Table 14-28 lists the channel parameters for a one-dimensional BD. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-43...
Page 588: Buffer Attributes (Bd_Attr)
For details on cyclic buffers, see Section 14.2, Buffer original value for a one-dimensional buffer. Types, on page 14-2. CONT Continuous Buffer Mode Buffer closes. Indicates whether buffer is to close when BD_SIZE reaches Buffer continues operating. zero. MSC8144E Reference Manual, Rev. 3 14-44 Freescale Semiconductor...
Page 589 Normal operation When size reaches zero, the channel can be frozen. The Freeze channel. already serviced requests continue normally. No further requests are issued for the associated channel until the host defrosts it. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-45...
Page 590 This 52-bit parameter holds the three-dimension parameters of the channel handling this buffer. It holds the base count value, current count, and address offset. The Multi Dimension fields are described in Table 14-33, BD_MD_3D Field Descriptions, on page 14-50. MSC8144E Reference Manual, Rev. 3 14-46 Freescale Semiconductor...
Page 591: Multi-Dimensional Buffer Attributes (Bd_Md_Attr)
When size reaches zero and CONT is set and the CONTD Next buffer port is MBus port 1. dimension count reaches zero, DMACHCR[SPRT] (for source buffers) or DMACHCR[DPRT] (for destination buffers) is updated according to the NPRT field. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-47...
Page 592 There is an automatic mask when ports are switched in a by MRD. continuous buffer. The DMA controller unmasks the requests when last data reaches the destination. See also the MRD field. MSC8144E Reference Manual, Rev. 3 14-48 Freescale Semiconductor...
Page 593 DMA task is completed. If CONT is set, CONTD < BD, and NPRT is different from the current port, MR must be set an MRD must be equal to CONTD. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 14-49...
Page 594 If the buffer is four dimensional, then this field cannot be 0. M4D_OFFSET Fourth Dimension Offset 27–0 Written in two’s complement. The offset is added to the BD_MD_ADDR each time BD_MD_SIZE, M2D_COUNT, and M3D_COUNT reach zero. MSC8144E Reference Manual, Rev. 3 14-50 Freescale Semiconductor...
Page 595 32-bit PCI interface support. Agent mode support. Supports accesses to all PCI address spaces. 64-bit dual-address cycle (DAC) support (as a target only). Internal configuration registers accessible from PCI and internal buses. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-1...
Page 596: Functional Description
PCI initiator mode is enabled by setting PCICCR[BMST]. As the target, the PCI controller acts as a bridge between the PCI bus and the MSC8144E interconnect. The PCI can be programmed to transfer transactions initiated by the PCI initiator to any of the following: M2 memory, M3 memory, DDR memory, or the configuration registers (CCSR).
Page 597: Bus Commands
As an initiator, 32-byte burst reads are translated either to a memory read line or memory read multiple depending on the configuration of C2GPR[PRCS] (see Chapter 4, Chip-Level Arbitration and Switching System (CLASS)). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-3...
Page 598: Pci Protocol Fundamentals
AD[31–2] incremented internally by 4 bytes until the end of the burst transfer. Another initiator in a memory access should drive 0b00 on during the address phase to indicate a linear AD[1–0] MSC8144E Reference Manual, Rev. 3 15-4 Freescale Semiconductor...
Page 599: Device Selection
(An idle cycle in PCI is when both PCI_FRAME are deasserted). Byte lanes not involved in the current data transfer are driven to a stable PCI_IRDY condition even though the data is not valid. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-5...
Page 600: Bus Transactions
Figure 15-1 shows an example of a single beat read transaction. PCI_CLK PCI_AD[31–0] ADDR DATA PCI_C/BE[3–0] BYTE ENABLES PCI_FRAME PCI_IRDY PCI_DEVSEL PCI_TRDY Figure 15-1. Single Beat Read Example Figure 15-2 shows an example of a burst read transaction. MSC8144E Reference Manual, Rev. 3 15-6 Freescale Semiconductor...
Page 601 Figure 15-3 shows an example of a single beat write transaction. PCI_CLK PCI_AD[31–0] ADDR DATA PCI_C/BE[3–0] BYTE ENABLES PCI_FRAME PCI_IRDY PCI_DEVSEL PCI_TRDY Figure 15-3. Single Beat Write Example Figure 15-4 shows an example of a burst write transaction. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-7...
Page 602: Transaction Termination
PCI_TRDY PCI_STOP more data is transferred, and the initiator therefore does not have to wait for a final data transfer (see the retry diagram in Figure 15-5). MSC8144E Reference Manual, Rev. 3 15-8 Freescale Semiconductor...
Page 603 A cache line wrap transaction has completed a cache line transfer. Another target-initiated termination is the retry termination. Retry refers to termination requested because the target is currently in a state where it is unable to process the transaction. This can MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-9...
Page 604: Other Bus Operations
For the first type (governed by the initiator), the initiator may only run a fast back-to-back transaction to the same target. For the second type, when the VCOP detects a fast-back-to-back MSC8144E Reference Manual, Rev. 3 15-10 Freescale Semiconductor...
Page 605: Dual Address Cycles
A disconnect occurs if the VCOP runs out of buffer space on writes, or the VCOP cannot supply consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also occurs if the transaction crosses a 4K page boundary. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-11...
Page 606: Configuration Access
When the CONFIG_DATA register is written, the VCOP generates a special cycle encoding on the command/byte enable lines during the address phase, and drives the data from the CONFIG_DATA register onto the address/data lines during the first data phase. MSC8144E Reference Manual, Rev. 3 15-12 Freescale Semiconductor...
Page 607: Interrupt Acknowledge
( asserted) involving the VCOP. When an address or PCI_IRDY PCI_TRDY data parity error is detected, the detected-parity-error bit in the configuration space status register is set (see page 15-24 for details). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-13...
Page 608: Error Reporting
VCOP completes the transaction on the PCI bus even if a data parity error occurs. If parity error occurs during a write to system memory, the transaction completes on the PCI bus but is aborted internally, insuring that potentially corrupt data does not go to memory. MSC8144E Reference Manual, Rev. 3 15-14 Freescale Semiconductor...
Page 609: Pci Inbound Address Translation
PCI inbound translation windows may not overlap or be translated to the PCI Outbound Window (0xE0000000 to 0xE7FFFFFF in the local memory space). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-15...
Page 610: Pci Outbound Address Translation
PCI memory or I/O space. Translation window base addresses are defined in the PCI outbound base address registers. See page 15-44 for details. Transactions to these address ranges are issued on the PCI bus with a translated address. The translation addresses are defined MSC8144E Reference Manual, Rev. 3 15-16 Freescale Semiconductor...
Page 611: Transaction Ordering
Inbound writes that originated on the PCI port and were posted before the read data arrives from the PCI. The PCI is always able to accept an Inbound write transaction from PCI port without forcing the PCI port to first accept an Outbound read. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-17...
Page 612: Initialization Sequence
Base Class Code Configuration Register (BCCCR), see page 15-26 Cache Line Size Configuration Register (CLSCR), see page 15-27 Latency Timer Configuration Register (LTCR), see page 15-27 Header Type Configuration Register (HTCR), see page 15-28 MSC8144E Reference Manual, Rev. 3 15-18 Freescale Semiconductor...
Page 613 PCI Outbound Base Address Registers 0–5 (POBAR[0–5]), see page 15-44 PCI Outbound Comparison Mask Registers 0–5 (POCMR[0–5]), see page 15-44 Discard Timer Control Register (DTCR), see page 15-46 Note: The PCI memory-mapped registers use a base address of: 0xFFF7A000. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-19...
Page 614: Pci Configuration Access Registers
00000 Transactions to PCI internal configuration space 15–11 Although these bits are writable, only the values 0 enabled. and 31 are legal. 11111 Special cycles and interrupt acknowledge transactions enabled. All other values are invalid. MSC8144E Reference Manual, Rev. 3 15-20 Freescale Semiconductor...
Page 615: Pci Configuration Data Register (Config_Data)
15-4 shows the CONFIG_DATA bit field. Table 15-4. CONFIG_DATA Field Descriptions Bits Description CFG_DATA Configuration Data 31–0 Contains data used for transactions to the PCI controller internal configuration space and for special cycle transactions. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-21...
Page 616: Pci Interrupt Acknowledge Register (Pci_Int_Ack)
Table 15-6 shows the bit settings of the VIDCR. Table 15-5. DIDCR Field Descriptions Bits Description Vendor ID 15–0 This field identifies the vendor ID. For Freescale Semiconductor, the VID is 0x1957. MSC8144E Reference Manual, Rev. 3 15-22 Freescale Semiconductor...
Page 617: Device Id Configuration Register (Didcr)
Parity errors ignored This bit controls the VCOP response to a parity error. Standard parity error handling — Reserved. Write to 0 for future compatibility. The field is hard-wired to 0 internally MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-23...
Page 618: Pci Status Configuration Register (Pciscr)
(as controlled by bit 6 in the PCI Command register). SSERR Signaled System Error PCI_SERR not asserted This bit is set whenever PCI asserts PCI_SERR. PCI_SERR asserted MSC8144E Reference Manual, Rev. 3 15-24 Freescale Semiconductor...
Page 619: Revision Id Configuration Register (Ridcr)
The value of this register is represented by x in the register diagram. Table 15-9 shows the bit settings of the RIDCR. Table 15-9. RIDCR Field Descriptions Bits Description Revision ID 7–0 This field specifies a revision code for the PCI controller. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-25...
Page 620: Standard Programming Interface Configuration Register (Spicr)
15.2.2.8 Base Class Code Configuration Register (BCCCR) BCCCR Base Class Code Configuration Register Offset 0x0B Type Reset This is the upper byte of the class code. Table 15-12 shows the bit settings of the BCCCR. MSC8144E Reference Manual, Rev. 3 15-26 Freescale Semiconductor...
Page 621: Cache Line Size Configuration Register (Clscr)
Refer to the PCI 2.2 specification for the rules by which the VCOP completes transactions when the timer has expired. — Reserved. Write to 0 for future compatibility. The field is hard-wired to 0 internally 2–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-27...
Page 622: Header Type Configuration Register (Htcr)
This field defines the low portion of the base address for the internal memory-mapped register space. Prefetchable This read-only bit is hardwired internally to 0. Type 2–1 Hard-wired internally to 00. Memory Space Indicator Hard-wired internally to 0. MSC8144E Reference Manual, Rev. 3 15-28 Freescale Semiconductor...
Page 623: Gpl Base Address Register 0 (Gplbar0)
Hard-wired internally to 00. Memory Space Indicator Hard-wired internally to 0. 15.2.2.15 GPL Base Address Registers 1–2 (GPLBAR[1–2]) GPLBAR1 GPL Base Address Registers 1–2 Offset 0x18 GPLBAR2 Offset 0x20 Type Reset — Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-29...
Page 624: Gpl Extended Base Address Registers 1–2 (Gplextbar[1–2])
PIBAR[1–2]/PIEBAR[1–2]. Note that this write operation does not change the bits that are masked by the IWS field. For read operations, these masked bits always return zeros. Table 15-18 shows the GPLEXTBAR[1–2] bit field. MSC8144E Reference Manual, Rev. 3 15-30 Freescale Semiconductor...
Page 625: Sub-System Vendor Id Configuration Register (Svidcr)
Table 15-20 shows the bit settings of the SDIDCR. Table 15-20. SDIDCR Field Descriptions Bits Description Settings SDID Sub-System Device ID 15–0 This field identifies the board or sub-system that contains this device. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-31...
Page 626: Capabilities Pointer Configuration Register (Capptrcr)
Offset 0x3D INT_PIN Type Reset Table 15-22 shows the bit settings of the INTPINCR. Table 15-22. INTPINCR Field Descriptions Bits Description Settings INT_PIN Interrupt Pin 7–0 This field is hard-wired to 0x00. MSC8144E Reference Manual, Rev. 3 15-32 Freescale Semiconductor...
Page 627: Min Gnt Configuration Register (Mingntcr)
This bit controls access to the PCI configuration space from the PCI spaces is permitted. port. Any inbound PCI access to the PCI configuration space is retried. — Reserved. Write to 0 for future compatibility. 4–3 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-33...
Page 628: Pci Memory-Mapped Control And Status Registers
30–11 APAR Address Parity Error No error This bit is set when there is an address parity error on a PCI access Error detected initiated by a device other than this VCOP. MSC8144E Reference Manual, Rev. 3 15-34 Freescale Semiconductor...
Page 629: Pci Error Capture Disable Register (Pci_Ecdr)
Table 15-25. PCI_ECDR Field Descriptions Bits Description Settings — Reserved. Write to 0 for future compatibility. 31–11 APAR Address Parity Error Capture is enabled. This bit disables capture for an address parity error. Capture is disabled. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-35...
Page 630: Pci Error Enable Register (Pci_Eer)
Generates an interrupt when the corresponding bit in the PCI_ESR is Interrupt generated. set. MPERR Initiator Parity Error No interrupt. Generates an interrupt when the corresponding bit in the PCI_ESR is Interrupt generated. set. MSC8144E Reference Manual, Rev. 3 15-36 Freescale Semiconductor...
Page 631: Pci Error Attributes Capture Register (Pci_Earcr)
This field is encoded to indicate the type of the first PCI error captured. Write data parity error Read data parity error Initiator abort Target abort System error indication received Parity error indication received on a read Parity error indication received on a write MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-37...
Page 632 This bit contains the PCI parity bit for the captured data word. Error Information Valid No valid error information The bit indicates that the error information captured in this register, Error information is valid PCI_EACR, PCI_EEACR, and PCI_EDCR is valid. MSC8144E Reference Manual, Rev. 3 15-38 Freescale Semiconductor...
Page 633: Pci Error Address Capture Register (Pci_Eacr)
Table 15-29 shows the PCI_EEACR bit field. Table 15-29. PCI_EEACR Field Descriptions Bits Description PCI_EEA PCI Error Extended Address 31–0 Contains the high portion of the address associated with the first detected error. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-39...
Page 634: Pci Error Data Low Capture Register (Pci_Edlcr)
Reserved. Write to 0 for future compatibility. 31–20 Translation Address 19–0 This field contains the starting address of the inbound translated address. This 20-bit field corresponds to bits 31–12 of a 32-bit address. MSC8144E Reference Manual, Rev. 3 15-40 Freescale Semiconductor...
Page 635: Pci Inbound Base Address Registers 0–2 (Pibar[0–2])
Offset 0x05C — Type Reset Type Reset PIEBAR[1–2] define the high portion of the starting point of the inbound windows in the PCI memory space. Table 15-33 shows the PIEBAR[1–2] bit fields. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-41...
Page 636: Pci Inbound Window Attribute Registers 0–2 (Piwar[0–2])
001011 4-Kbyte window size Inbound translation window size N which is the encoded 2^(N+1) bytes 001100 8-Kbyte window size window size. The smallest window is 4 Kbytes (N = 11). 011110 2-Gbyte window size 011111–111111Reserved MSC8144E Reference Manual, Rev. 3 15-42 Freescale Semiconductor...
Page 637: Pci Outbound Translation Address Registers 0–5 (Porar[0–5])
Reserved. Write to 0 for future compatibility. 31–20 Translation Address 19–0 This field contains the starting address of the outbound translated address. This 20-bit field corresponds to bits 31–12 of a 32-bit address. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-43...
Page 638: Pci Outbound Base Address Registers 0–5 (Pobar[0–5])
15.2.4.14 PCI Outbound Comparison Mask Registers 0–5 (POCMR[0–5]) POCMR0 PCI Outbound Comparison Mask Registers 0–5 Offset 0x110 POCMR1 Offset 0x128 POCMR2 Offset 0x140 POCMR3 Offset 0x158 POCMR4 Offset 0x170 POCMR5 Offset 0x188 — Type Reset Type Reset MSC8144E Reference Manual, Rev. 3 15-44 Freescale Semiconductor...
Page 639 8 MB 1111_1111_1100_0000_0000 4 MB 1111_1111_1110_0000_0000 2 MB 1111_1111_1111_0000_0000 1 MB 1111_1111_1111_1000_0000 512 KB 1111_1111_1111_1100_0000 256 KB 1111_1111_1111_1110_0000 128 KB 1111_1111_1111_1111_0000 64 KB 1111_1111_1111_1111_1000 32 KB 1111_1111_1111_1111_1100 16 KB 1111_1111_1111_1111_1110 8 KB MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 15-45...
Page 640: Discard Timer Control Register (Dtcr)
PCI initiator has not repeated the transaction in 2 PCI clocks, Note: Assuming the internal frequency is twice the PCI frequency, the PTV should equal 2 – 2 (0xFF0000). MSC8144E Reference Manual, Rev. 3 15-46 Freescale Semiconductor...
Page 641 It handshakes with the software running on a DSP core through buffer descriptors (BDs) that are messaged from the DSP core to the host. The host can put all the data buffers into its memory and have the MSC8144E access the data.
Page 642: Introduction
Serial RapidIO Controller The MSC8144E can perform NREAD, NWRITE, NWRITE_R, SWRITE, or MAINTENANCE accesses to any device directly connected to it, or to any other device that is part of the RapidIO interconnection through RapidIO switches. This capability is in addition to the MESSAGES and DOORBELL transactions already described.
Page 643 Logical outbound packet time-to-live counter to prevent local processor from hanging when the RapidIO interface fails. Accept-all mode of operation for failover support. RapidIO random bit error injection. Performance monitor interface for selected events. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-3...
Page 644: Operating Modes
Transmission rates of 1.25. 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps, respectively). Small or large size transport information field. Accept-all mode of operation; all packets are accepted regardless of the target ID. MSC8144E Reference Manual, Rev. 3 16-4 Freescale Semiconductor...
Page 645: X/4X Lp-Serial Signals
This section summarizes the RapidIO transactions, packet format, and control symbols. It also discusses how the configuration registers are accessed via the RapidIO packets and the operation of the ATMU translation windows for translating RapidIO addresses to local physical addresses and vice versa. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-5...
Page 646: Rapidio Transactions
0000 Message done response 0011 Message retry response 0111 Message error response 16.2.2 RapidIO Packet Format Table 16-4 summarizes the small transport field packet formats of RapidIO transaction types for LP-Serial operation. MSC8144E Reference Manual, Rev. 3 16-6 Freescale Semiconductor...
Page 647 RapidIO endpoint limits configuration read and write requests to 32-bit data accesses. The large transport field packet format extends the destination and source IDs to 16-bits each. The MSC8144E supports small and large transport fields (large at default), so, for large transport, the destination and source IDs are 16-bits wide according to the direction of the transaction.
Page 648: Rapidio Control Symbol Summary
00010 Received a control symbol with bad CRC. 00011 Non-maintenance packet reception is stopped. 00100 Received packet with bad CRC. 00101 Received invalid character or a valid but illegal character. 11111 General error. MSC8144E Reference Manual, Rev. 3 16-8 Freescale Semiconductor...
Page 649 — End of packet — Restart from retry — Link request cmd: Reset the receiving device Return input port status; functions as a restart-from-error control symbol under error conditions — NOP (ignore) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-9...
Page 650: Accessing Configuration Registers Via Rapidio Packets
The LCSBACSR hit definition and RapidIO address translation are as follows: device_ccsrbar_size = 0 (size is 1 MB)—as defined for the MSC8144E — A window hit is defined as LCSBA1CSR[30–17] matching RapidIO address [0–13].
Page 651: Rapidio Maintenance Accesses
MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-11...
Page 652: Outbound Maintenance Accesses
The RapidIO endpoint implementation allows up to a 34-bit (0–33) RapidIO address and a 36-bit (0–35) internal interconnection address. The MSC8144E is confined to 32-bit internal addresses, therefore the top 4 bits (0–3) of the Inbound translation address and the outbound base address should be set to all 0;...
Page 653: Rapidio Outbound Atmu
= 0x05. A write to offset 0x0 in segment 2 is also translated, to the same offset in the target device as the write to segment 0, but this time a NWRITE_R transaction is generated. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 654: Outbound Windows
RapidIO address translation and specify the RapidIO destination ID for the transaction. Port n RapidIO Outbound Window Attributes Registers 0–8 define the translation window size and specify the RapidIO transaction type and priority for the transaction. MSC8144E Reference Manual, Rev. 3 16-14 Freescale Semiconductor...
Page 655: Window Size And Segmented Windows
— A window hit is defined as {BEXADD[0–3]} matching internal address [0–3] — RapidIO addr[0–30] = {TREXAD[8–9], internal address[4–32]} 8G window size — A window hit is defined as {BEXADD[0–2]} matching internal address [0–2] MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-15...
Page 656 IDs per segment (8 total) , 1, 2, 3 , 1, 2, 3 with TGTID[6–7] Segmented windows generating defined by the sub-segment # four target IDs per segment (16 total) MSC8144E Reference Manual, Rev. 3 16-16 Freescale Semiconductor...
Page 657: Valid Hits To Multiple Atmu Windows
Figure 16-4. Valid Hit that Extends Into a Lower Priority Window If a request hits (base address match) multiple ATMU windows (1–8) and the transaction end address extends beyond the boundary of a lower priority hit window but MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-17...
Page 658: Window Boundary Crossing Errors
The RapidIO endpoint handles this as follows: If a request hits (base address match) an ATMU window (1–8, default) and the transaction end address extends into another ATMU window with higher priority, an MSC8144E Reference Manual, Rev. 3 16-18 Freescale Semiconductor...
Page 659 The outbound request is discarded. Window #0 (default window) Window #2 Transaction start address Transaction end address Figure 16-8. Boundary Crossing Error Due to Transaction Size Exceeding the Window Size MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-19...
Page 660: Rapidio Inbound Atmu
• NREAD, NWRITE_R request misses all four Port 0 RapidIO Inbound Window P0RIWAR0 page 16-166 ATMU comparison windows and the Attributes Register 0 LCSBA1CSR window. • NWRITE, SWRITE request misses all four comparison windows. MSC8144E Reference Manual, Rev. 3 16-20 Freescale Semiconductor...
Page 661: Hits To Multiple Atmu Windows
If a request hits multiple ATMU windows, window 1 has the highest priority of the five inbound ATMU windows (windows 1–4, default). Window 2 has the next highest priority, followed by windows 3 and 4. The default window has the lowest priority. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-21...
Page 662: Window Boundary Crossing Errors
LTLEDCSR[IACB] configuration register. If a request misses all ATMU windows (1–4) and the transaction end address exceeds the maximum size of the default window, an inbound ATMU crossed boundary error is not generated. MSC8144E Reference Manual, Rev. 3 16-22 Freescale Semiconductor...
Page 663: Generating Link-Request/Reset-Device
The RapidIO port is placed into Drain mode when one of the following occurs: PnPCR[OBDEN] is set. he Failed Threshold has been encountered and the PnCCSR[SPF] and PnCCSR[DPE] are both set The packet time-to-live counter expires causing PnPCR[OBDEN] to be set MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-23...
Page 664: Input Port Disable Mode
Output Port Disable mode at the same time, however, some packet acknowledgements may be discarded by the RapidIO port. If the inbound ackID is not accepted, software should change it before taking the RapidIO port out of Input Port Disable mode. MSC8144E Reference Manual, Rev. 3 16-24 Freescale Semiconductor...
Page 665: Software Assisted Error Recovery Register Support
This section describes how the logical and physical layers detect RapidIO errors and respond to them. For details on the action of the SC3400 core when it is notified of any of these errors, see MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 666: Rapidio Error Description
Table 16-8 lists all the RapidIO link errors detected by the RapidIO endpoint physical layer and the actions taken by the RapidIO endpoint. The Error Enable column lists the control bits that can MSC8144E Reference Manual, Rev. 3 16-26 Freescale Semiconductor...
Page 667 Enable/Detect column indicates which bit of the P0ERECSR (see page 16-137) allows the error to increment the error rate counter and lock the Port 0 Error Capture registers—and also which P0EDCSR bit is set when the error is detected (see page 16-136). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-27...
Page 668 Error state. (unexpected packet/contr ol symbol received) Received packet with a bad P0PCR[CCP] Enter input error 4: bad CRC on Received CRC value. enables stopped. packet. packet with detect. bad CRC MSC8144E Reference Manual, Rev. 3 16-28 Freescale Semiconductor...
Page 669 [TV] > 0 stopped. time-out interval. enables detect. A Link response is not PLTOCCSR (re-) Enter output received within the specified [TV] > 0 error stopped. time-out interval enables detect. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-29...
Page 670: Logical Layer Rapidio Errors
Otherwise, no error response is sent. For multiple errors, a discard of a packet has a higher priority than an error response. For misaligned transactions, the error management extension registers are updated with each child. MSC8144E Reference Manual, Rev. 3 16-30 Freescale Semiconductor...
Page 671 16 bytes for large transport packet. is set Large transport packet has 14 valid bytes and two bytes of padding of 0s. Padding of 0s is not checked. PayloadSize Not Applicable. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-31...
Page 672 Reserved transaction type for this ftype LTLEECSR[ITD] packet is is set. dropped. RdSize Yes if LTLEDCSR[ITD] Read/Write request size is not for 4 bytes. LTLEECSR[ITD] is set. SrcTID Not checked for error. MSC8144E Reference Manual, Rev. 3 16-32 Freescale Semiconductor...
Page 673 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-33...
Page 674 Not Checked for error. Address:WdPtr:Xambs Yes if LTLEECSR[ITD] is LTLEDCSR[ITD] Yes for NWRITE_R address matches set. NWRITE_R. LCSBA1CSR with a request that is not a 32-bit read. Performed only for NWRITE_R packet. MSC8144E Reference Manual, Rev. 3 16-34 Freescale Semiconductor...
Page 675 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-35...
Page 676 16.2.5.4.2, Window Boundary Crossing Errors, on page 16-22. Address:WdPtr:Xambs Yes if LTLEECSR[ITD] is set. LTLEDCSR[ITD] RapidIO Request hits a protected ATMU packet is window or the local configuration dropped. space window. MSC8144E Reference Manual, Rev. 3 16-36 Freescale Semiconductor...
Page 677 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-37...
Page 678 12 bytes for small transport packet or is less than 16 bytes for large transport packet. Padding of 0s for small or large transport packet is not verified. MSC8144E Reference Manual, Rev. 3 16-38 Freescale Semiconductor...
Page 679 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets bits 32–39. • LTLDIDCCSR[SID] gets bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-39...
Page 680 Reserved ssize field. Yes if LTLEECSR[MFE] LTLEDCSR[MFE] Yes if priority If priority is is set. is not 3. Else 3, packet is packet is dropped. dropped. MSC8144E Reference Manual, Rev. 3 16-40 Freescale Semiconductor...
Page 681 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets packet bits 56–63. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-41...
Page 682 • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets packet bits 56–63. For all entries except the first, the capture registers are loaded from the response RapidIO packet. MSC8144E Reference Manual, Rev. 3 16-42 Freescale Semiconductor...
Page 683 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-43...
Page 684 DMA response. Header size is not 8 bytes for small is set. dropped and transport packet or not 12 bytes for large transport ignored. packet. Two byte padding of 0s in a large transport field packet is not checked. MSC8144E Reference Manual, Rev. 3 16-44 Freescale Semiconductor...
Page 685 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-45...
Page 686 24, 32, 40, 48, 56, or 64 bytes). Payload size is greater than the value defined by wr_size. Payload size is not 64-bit aligned when the wr_size is not 4 bytes. MSC8144E Reference Manual, Rev. 3 16-46 Freescale Semiconductor...
Page 687 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-47...
Page 688 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 16-48 Freescale Semiconductor...
Page 689 • LTLDIDCCSR[DID] gets packet bits 24–31. • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-49...
Page 690 • LTLDIDCCSR[SIDMSB] gets packet bits 32–39. • LTLDIDCCSR[SID] gets packet bits 40–47. • LTLCCCSR[FT] gets packet bits 12–15. • LTLCCCSR[TT] gets packet bits 48–51. • LTLCCCSR[MI] gets 0s. • LTLCCCSR[MI] gets 0s. MSC8144E Reference Manual, Rev. 3 16-50 Freescale Semiconductor...
Page 691: Rapidio Message Unit
One entire message with up to a 16 message segments can be transmitted before a response is received. One entire single-segment message to all multicast destinations (up to 32) can be transmitted before a response is received. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-51...
Page 692: Outbound Message Controller Operation
OMxMR[MUS] changes from 0 to 1 and the outbound message controller is not busy. If it is busy, OMxMR[MUS] the transition from 0 to 1 is ignored. Software should program all the appropriate registers before setting OMxMR[MUS]. MSC8144E Reference Manual, Rev. 3 16-52 Freescale Semiconductor...
Page 693 (OMxSAR). If a message has multiple segments, the outbound message controller reads the other message segments from local memory. After the message read to local memory completes, the message is sent. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-53...
Page 694 • A packet response time-out occurs and this interrupt event is enabled (OMxMR[EIE]). • A retry threshold exceeded error occurs and this interrupt event is enabled (OMxMR[EIE]). • An internal error response is received and this interrupt event is enabled (OMxMR[EIE]). MSC8144E Reference Manual, Rev. 3 16-54 Freescale Semiconductor...
Page 695: Software Error Handling
Disables the message controller by clearing OMxMR[MUS]. Clears the error by writing a 1 to the corresponding OMxSR status bit (see Table 16-104, OMxSR Field Descriptions, on page 16-170): • MER • PRT • RETE • TE MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-55...
Page 696: Disabling And Enabling The Message Controller
These error condition checks are provided by the messaging unit in addition to the error condition checks provided by the RapidIO port described in Section 16.2.10, Errors and Error Handling, on page 16-25. MSC8144E Reference Manual, Rev. 3 16-56 Freescale Semiconductor...
Page 697 Status bit set: Illegal transaction decode in the Logical/Transport Layer Error Detect CSR LTLEDCSR[ITD]. Message segment sent: Yes Logical/Transport Layer Capture Register: Updated with the packet. Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-57...
Page 698 CSR LTLEDCSR[MER]. OMxSR[MER] bit is set in Direct mode or Chaining mode. Message segment sent: Yes Logical/Transport Layer Capture Register: Updated with the corresponding message request packet. Comments: Message segment transfer complete. The descriptor dequeue pointer is not incremented in chaining mode. MSC8144E Reference Manual, Rev. 3 16-58 Freescale Semiconductor...
Page 699 0 if the message response packet is captured. • LTLCCCSR[MI] gets the message information (packet bits 56–63). Table 16-25 lists programming errors that result in undefined or undesired hardware operation. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-59...
Page 700: Chaining Mode
Local Memory Interface Message Outbound Data Message Message Controller Enqueue Pointer Data Descriptor Descriptor Message Descriptor Dequeue Pointer Data Descriptor Message Data Outbound Descriptor List Queue Figure 16-9. Outbound Frame Queue Structure MSC8144E Reference Manual, Rev. 3 16-60 Freescale Semiconductor...
Page 701 When the descriptor queue is not empty, the message controller reads the descriptor from local memory using the address to which the dequeue pointer (OMxDQDPAR) is pointing and sets the busy bit (OMxSR[MUB]). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-61...
Page 702 (OMxSR[PRT]). If OMxMR[EIE] is set, the interrupt Serial RapidIO error/write-port is generated. If the retry error threshold value is exceeded for a specific segment, the retry error threshold exceeded bit is set (OMxSR[RETE]) and outbound message controller MSC8144E Reference Manual, Rev. 3 16-62 Freescale Semiconductor...
Page 703: Changing Descriptor Queues In Chaining Mode
× 32 byte (the size of each queue descriptor). For each descriptor in the queue, the message unit controller starts MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 704: Chaining Mode Controller Interrupts
= 1). The event causing the outbound message interrupt is indicated by OMxSR[QEI]. The interrupt is held until the queue is not empty and the OMxSR[QEI] bit is cleared by writing a value of 1 to it. MSC8144E Reference Manual, Rev. 3 16-64 Freescale Semiconductor...
Page 705 Retry Error Threshold Exceeded • Sets the retry threshold exceed status bit (OMxSR[RETE]) • Generates the Serial RapidIO error/write-port interrupt if OMxMR[EIE] is set. • Stops after the message operation completes (indicated by OMxSR[MUB]). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-65...
Page 706: Software Error Handling
Verifies that the message controller has stopped by polling OMxSR[MUB]. Disables the message controller by clearing OMxMR[MUS]. Clears the error by writing a 1 to the corresponding OMxSR status bit (listed in step 1). MSC8144E Reference Manual, Rev. 3 16-66 Freescale Semiconductor...
Page 707: Hardware Error Handling
Undefined operation outside of queue Enqueueing of descriptors causes descriptor queue Outbound message Queue overflow Message controller overflow interrupt enable set (OMxSR[QOI]) stops. (OMxMR[QOIE]) Queue misaligned May result in duplicate messages being sent. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-67...
Page 708: Outbound Message Controller Arbitration
(IMxMR[MI]]), causing the dequeue pointer to point to the next message frame in the queue, or wait until all received messages are processed and write to the dequeue pointer. MSC8144E Reference Manual, Rev. 3 16-68 Freescale Semiconductor...
Page 709: Inbound Message Controller Initialization
In the inbound message mode register (IMxMR), set the mailbox enable bit (IMxMR[ME]) along with the other control parameters (frame queue size, message-in-queue threshold, frame size, snoop enable, and the various interrupt enables). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-69...
Page 710: Inbound Controller Operation
An inbound message interrupt is generated to the local processor if the number of messages in the queue is greater than or equal to the configured message-in-queue threshold (IMxMR[MIQ_THRESH) and this event is enabled to generate the interrupt (IMxMR[MIQIE]). MSC8144E Reference Manual, Rev. 3 16-70 Freescale Semiconductor...
Page 711: Message Steering
16.3.3.5 Inbound Message Controller Interrupts The inbound message controller generates the inbound message interrupt for several different events. Each event can be individually enabled: Message-In-Queue interrupt is generated under one of the following conditions: MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-71...
Page 712: Software Error Handling
• Generates the Serial RapidIO error/write-port interrupt if IMxMR[EIE] is set. 16.3.3.6 Software Error Handling When an error occurs and the Serial RapidIO error/write-port interrupt is generated, software takes the following actions: MSC8144E Reference Manual, Rev. 3 16-72 Freescale Semiconductor...
Page 713: Hardware Error Handling
These error condition checks are provided by the messaging unit. These check are in addition to the error condition checks provided by the RapidIO port and described in Section 16.2.10, Errors and Error Handling, on page 16-25. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-73...
Page 714 Status bit set: Message Format error in the Logical/Transport Layer Error Detect CSR LTLEDCSR[MFE]. Queue entry written in local memory: No Response status: Error Logical/Transport Layer Capture Register: Updated with the packet Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 16-74 Freescale Semiconductor...
Page 715 Status bit set: Message format error in the Logical/Transport Layer Error begins. Detect CSR LTLEDCSR[MFE]. Queue entry written in local memory: No Response status: Error Logical/Transport Layer Capture Register: Updated with the packet. Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-75...
Page 716 Message failed in the Message CSR (MCSR[FA]). Queue entry written in local memory: No Response status: Error Logical/Transport Layer Capture Register: Comments: Message controller stops after the current message operation completes. The enqueue pointer is not incremented. MSC8144E Reference Manual, Rev. 3 16-76 Freescale Semiconductor...
Page 717 • LTLDIDCCSR[SID] gets the least significant byte of the source ID (packet bits 40–47) • LTLCCCSR[FT] gets the ftype (packet bits 12–15) • LTLCCCSR[TT] gets the ttype (packet bits 48–51) • LTLCCCSR[MI] gets the msg info (packet bits 56–63). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-77...
Page 718: Programming Errors
If the message controller is disabled before all of the message segments for a multisegment message are received, a message request time-out must occurs and all pending frame queue writes must complete before message busy clears (IMxSR[MB]). MSC8144E Reference Manual, Rev. 3 16-78 Freescale Semiconductor...
Page 719: Rapidio Message Passing Logical Specification Register Bits
The doorbell controllers are controlled through a set of run-time registers. 16.4.1 Features Support for one outbound doorbell controllers Support for one inbound doorbell controllers The doorbell controller can sustain back-to-back inbound doorbells MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-79...
Page 720: Doorbell Controller
Doorbell Controller The RapidIO architecture specification defines a doorbell type with no data payload that is transferred using inbound and outbound doorbell controllers. The MSC8144E RapidIO interconnect doorbell unit supports both inbound and outbound doorbells. The doorbell entry size is fixed at 64 bits because doorbell packets only pass a small amount of information, making the enqueue and dequeue pointers double-word addresses.
Page 721: Outbound Doorbell Controller
• Done response received. • Error response received. • Packet response time-out. • Retry limit exceeded. The outbound doorbell interrupt is generated if the end of doorbell outbound doorbell interrupt event is enabled (ODDATR[EODIE]). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-81...
Page 722: Interrupts
Disables the doorbell controller by clearing ODMR[DUS]. Clears the error by writing a 1 to the corresponding ODSR status bit (see Table 16-120, ODSR Field Descriptions, on page 16-188): • MER • PRT MSC8144E Reference Manual, Rev. 3 16-82 Freescale Semiconductor...
Page 723: Hardware Error Handling
Status bit set: Transport size error in the Logical/Transport Layer Error Detect CSR LTLEDCSR[TSE] (see page 16-131). Doorbell sent: Yes. Logical/Transport Layer Capture Register: Updated with the packet. Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-83...
Page 724 Status bit set: Illegal transaction decode in the Logical/Transport Layer Error Detect CSR LTLEDCSR[ITD] (see page 16-131). Doorbell sent: Yes Logical/Transport Layer Capture Register: Updated with the packet. Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 16-84 Freescale Semiconductor...
Page 725 Doorbell sent: Yes Logical/Transport Layer Capture Register: Updated with the doorbell request packet in RapidIO endpoint. Comments: Doorbell transfer complete. Note that RapidIO endpoint sends a special priority 3 packet indicating a doorbell time-out. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-85...
Page 726: Programming Errors
(IDMR[DI]]) causing the dequeue pointer to point to the next doorbell in the queue or wait until all the received doorbells are processed and write the dequeue pointer. MSC8144E Reference Manual, Rev. 3 16-86 Freescale Semiconductor...
Page 727 (IDMR[DI]). Software determines whether there are more doorbells to process by reading the queue empty bit (IDSR[QE]). If the queue is not empty, the previous two steps are repeated. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-87...
Page 728: Doorbell Queue Entry Format
RapidIO port can be configured to accept packets from any destination. When there are multiple RapidIO ports on one device, each port can be configured with a different destination ID. For the MSC8144E, the target information is identical for all received doorbell entries. Table 16-37. Inbound Doorbell Target Info Definition...
Page 729: Retry Response Conditions
When an internal error occurs while the doorbell controller is writing to local memory the doorbell controller responds as follows: Sets the transaction error bit (IDSR[TE]) and enters the error state. Returns an error response. Generates the Serial RapidIO error/write-port interrupt if IDMR[EIE] is set. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-89...
Page 730: Software Error Handling
Status bit set: Transport size error in the Logical/Transport Layer Error Detect CSR LTLEDCSR[TSE]. Queue Entry Written in local memory: No Response status: No response Logical/Transport Layer Capture Register: Updated with packet. Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 16-90 Freescale Semiconductor...
Page 731 Error checking level: 3 disabled and doorbell Interrupt generated: No received Status bit set: None Queue Entry Written in local memory: No Response status: Error Logical/Transport Layer Capture Register Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-91...
Page 732 • LTLDIDCCSR[SID] gets the least significant byte of the source ID (packet bits 40–47). • LTLCCCSR[FT] gets the ftype (packet bits 12–15). • LTLCCCSR[TT] gets the ttype (packet bits 48–51). • LTLCCCSR[MI] gets 0. MSC8144E Reference Manual, Rev. 3 16-92 Freescale Semiconductor...
Page 733: Programming Errors
Before the doorbell controller is reenabled, the doorbell busy bit must be clear (IDSR[DB) and the doorbell dequeue pointer address register (DQDPAR) and the doorbell queue enqueue pointer address register (DQEPAR) must be initialized to the same value for proper doorbell controller operation. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-93...
Page 734: Rapidio Message Passing Logical Specification Registers
The port-write controller uses the error/port-write interrupt for the RapidIO error/write-port to indicate incoming port-writes. Local Memory Local Processor Read Pointer Port-Write Inbound Pointer Port-write 64-Byte Entry Port-Write Packets from Controller RapidIO interface Port Write Queue Figure 16-14. Inbound Port-Write Structure MSC8144E Reference Manual, Rev. 3 16-94 Freescale Semiconductor...
Page 735: Port-Write Controller Initialization
Software processes the port-write queue entry to which the port-write base address registers (IPWQBAR) are pointing. Software sets the clear queue bit (IPWMR[CQ]) to reenable the hardware to receive another port-write. Software clears the queue full interrupt bit (IPWSR[QFI]) by setting IPWSR[QFI]. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-95...
Page 736: Port-Write Controller Interrupts
Disables the port-write controller by clearing IPWMR[PWE]. Clears the error by writing a 1 to the corresponding status bit (IPWSR[TE]). Disables, reinitializes, and reenables the port-write unit before another maintenance port-write can be received. MSC8144E Reference Manual, Rev. 3 16-96 Freescale Semiconductor...
Page 737: Hardware Error Handling
Queue Entry Written in local memory: No Response status: No response. Logical/Transport Layer Capture Register: Updated with packet. Comments: Packet is ignored and discarded. An error or illegal transaction target error response is not generated. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-97...
Page 738 Interrupt generated: No received Status bit set: None Queue Entry Written in local memory: No Response status: No response Logical/Transport Layer Capture Register: Comments: Packet is ignored and discarded. MSC8144E Reference Manual, Rev. 3 16-98 Freescale Semiconductor...
Page 739 An internal error response is returned. When the port-write controller receives the error response it sets the transaction error bit (IPWSR[TE]) and enters the error state. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-99...
Page 740: Disabling And Enabling The Port-Write Controller
Busy (PWDCSR[PB]). This bit reflects the state of the busy bit IPWnSR[PWB] Failed (PWDCSR[PFA]). This bit reflects the state of the transaction error status bit IPWnSR[TE] Error (PWDCSR[PE]). This bit is always a 0 MSC8144E Reference Manual, Rev. 3 16-100 Freescale Semiconductor...
Page 741: Rapidio Programming Model
— Logical/Transport Layer Error Detect Command and Status Register (LTLEDCSR), page 16-130 — Logical/Transport Layer Error Enable Command and Status Register (LTLEECSR), page 16-132 — Logical/Transport Layer Address Capture Command and Status Register (LTLACCSR), page 16-133 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-101...
Page 742 — Port 0 RapidIO Outbound Window Translation Address Register (P0ROWTARx), page 16-158 — Port 0 RapidIO Outbound Window Translation Extended Address Register (P0ROWTEARx), page 16-159 — Port 0 RapidIO Outbound Window Attributes Register (P0ROWARx), page 16-160 MSC8144E Reference Manual, Rev. 3 16-102 Freescale Semiconductor...
Page 743 — Outbound Doorbell Mode Register (ODMR), page 16-187 — Outbound Doorbell Status Register (ODSR), page 16-188 — Outbound Doorbell Destination Port Register (ODDPR), page 16-189 — Outbound Doorbell Destination Attributes Register (ODDATR), page 16-190 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-103...
Page 744: Device Identity Capability Register (Didcar)
0x1807 Device Identity 31–16 Uniquely identifies the type of device from the vendor specified by DVI. The values for DI are assigned and managed by the respective vendor. The value for the MSC8144E = 0x1807. 0x0002 Device Vendor Identity 15–0 Identifies the vendor that manufactures the device containing the processing element.
Page 745: Device Information Capability Register (Dicar)
Identifies the vendor that manufactures the assembly or subsystem containing the device. A value for AVI is uniquely assigned to an assembly vendor by the registration authority of the RapidIO Trade Association. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-105...
Page 746: Assembly Information Capability Register (Aicar)
0x0100 Extended Features Pointer 15–0 16.6.5 Processing Element Features Capability Register (PEFCAR) PEFCAR Processing Element Features Capability Register Offset 0x00010 BR MEM PROC SW — — TYPE RESET — CTLS TYPE RESET MSC8144E Reference Manual, Rev. 3 16-106 Freescale Semiconductor...
Page 747 PEFCAR identifies the major functionality provided by the processing element. Table 16-47. PEFCAR Field Descriptions Reset Description Settings Bridge Specifies whether the MSC8144E can bridge to another interface. Memory Specifies whether the MSC8144E has physically addressable local address space and can be accessed as an endpoint through non-maintenance operations.
Page 748: Source Operations Capability Register (Socar)
RESET SW NWR — — — TYPE RESET SOCAR defines the set of RapidIO logical operations that can be issued by the MSC8144E. Table 16-48. SOCAR Field Descriptions Reset Description Read Operation MSC8144E does not support. IRead Operation MSC8144E does not support.
Page 749: Destination Operations Capability Register (Docar)
RESET SW NWR — — — TYPE RESET DOCAR defines the set of RapidIO I/O operations that the MSC8144E can support as a target. Table 16-49. DOCAR Field Descriptions Reset Description Read Operation MSC8144E does not support. IRead Operation MSC8144E does not support.
Page 750 Atomic-Set Operation MSC8144E does not support. Atomic-Clr Operation MSC8144E does not support. — Reserved. Write to zero for future compatibility. Port-Write Operation Supported. — Reserved. Write to zero for future compatibility. 1–0 MSC8144E Reference Manual, Rev. 3 16-110 Freescale Semiconductor...
Page 751: Mailbox Command And Status Register (Mcsr)
1 return error responses. Full Not full. Specifies whether message controller 1 is full. When Full. FU0 is set, new messages to message controller 1 are retried. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-111...
Page 752: Port Write And Doorbell Command And Status Register (Pwdcsr)
Specifies whether the doorbell unit is full. When this bit is Full. set, new doorbell messages are retried. Empty Outstanding doorbell messages. Specifies whether the doorbell unit has outstanding No outstanding doorbell messages. doorbell messages. MSC8144E Reference Manual, Rev. 3 16-112 Freescale Semiconductor...
Page 753 When this bit is set, all incoming port-write transactions are discarded. Error This field always returns a value of 0. — Reserved. Write to zero for future compatibility. 1–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-113...
Page 754 PELLCCSR controls the extended addressing abilities. RapidIO endpoint supports only 34-bit addressing. Table 16-52. PELLCCSR Field Descriptions Reset Description — Reserved. Write to zero for future compatibility. 31–3 0b001 Extended Addressing Control 2–0 The read-only value of 0b001 specifies 34-bit addresses. MSC8144E Reference Manual, Rev. 3 16-114 Freescale Semiconductor...
Page 755 RESET LCSBA1CSR specifies the most significant bits of the local physical address double-word offset for the MSC8144E configuration register space allowing the configuration register space to be physically mapped in the processing element. This register allows configuration and maintenance of an MSC8144E through regular read and write operations rather than maintenance operations.
Page 756: Base Device Id Command And Status Register (Bdidcsr)
Large Base Device ID in Large Common Transport System 15–0 Valid only if PEFCAR[CTLS] is set. If the RapidIO controller is configured as a host, LBDID = 0x0000. If the RapidIO controller is configured as an agent, LBDID = 0xFFFF. MSC8144E Reference Manual, Rev. 3 16-116 Freescale Semiconductor...
Page 757 In this case, the register is reinitialized to 0xFFFF. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-117...
Page 758: Component Tag Command And Status Register (Ctcsr)
CTCSR contains a component tag value for the processing element that software can assign when the device is initialized. It is unused internally in RapidIO Endpoint. Table 16-56. CTCSR Field Descriptions Reset Description Component Tag 31–0 MSC8144E Reference Manual, Rev. 3 16-118 Freescale Semiconductor...
Page 759: Port Maintenance Block Header 0 (Pmbh0)
Therefore, the RapidIO Endpoint is defined here as not supporting software-assisted error recovery. Table 16-57. PMBH0 Field Descriptions Reset Description EFPTR 0x0600 Extended Features Pointer 31–15 EFID 0x0001 Extended Features ID 16–31 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-119...
Page 760 Clearing this field to all zeros disables the link time-out timer. This value is loaded each time the link time-out timer starts. — 0x00 Reserved. Write to 0x01 for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 16-120 Freescale Semiconductor...
Page 761 31–8 Clearing this field to all zeros disables the response time-out timer. This value is loaded each time the response time-out timer starts. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-121...
Page 762: Port General Control Command And Status Register (Pgccsr)
PGCCSR contains control register bits for the RapidIO interface. Note: The user must initialize the value of M to 1. Otherwise, no outbound transactions are initiated by the MSC8144E, including messages and doorbells. Table 16-60. PGCCSR Field Descriptions Reset Description...
Page 763 Contains the link request command to send. If read, this field returns the last written value. If written with a value other than 0x011 (reset device) or 0b100 (input status), the resulting operation is undefined. All other values are reserved in the RapidIO specification. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-123...
Page 764 Reserved. Write as zero for future compatibility. 30–10 AckID_Status 9–5 This field holds the AckID status field from the link response. Link Status 4–0 This field holds the link status field from the link response. MSC8144E Reference Manual, Rev. 3 16-124 Freescale Semiconductor...
Page 765: Port 0 Local Ackid Command And Status Register (P0Lascr)
Outbound ackID Output Port Next Transmitted ackID Value 4–0 This can be written by software but only if there are no outstanding unacknowledged packets. If there are, a newly-written value will be ignored MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-125...
Page 766: Port 0 Error And Status Command And Status Register (P0Escsr)
OR is set when ORS is set and cleared when a packet-accepted or packet-not-accepted control symbol is received. Read only. Output Stop The output port stops due to a retry. Read only. MSC8144E Reference Manual, Rev. 3 16-126 Freescale Semiconductor...
Page 767 The input and output ports are initialized and the port is exchanging error-free control symbols with the attached device. Read only. Ports Uninitialized Input and output ports are not initialized. This bit and PO are mutually exclusive. Read only. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-127...
Page 768: Port 0 Control Command And Status Register (P0Ccsr)
When OPE is cleared, the port routes or Port is enabled to issue packets. responds to I/O logical maintenance packets. Control symbols are not affected and are sent normally. The initial value of OPE is read from configuration pins. MSC8144E Reference Manual, Rev. 3 16-128 Freescale Semiconductor...
Page 769 This bit is hard-wired to 0. Error checking and recovery is disabled. Multicast Event Participant This bit is hard-wired to 0. The MSC8144E does not participate in multicast events. — Reserved. Write to zero for future compatibility. 18–4 Stop on Port Failed Encounter Enable Stop on port failed disabled.
Page 770: Error Reporting Block Header (Erbh)
The priority of errors is PRT and all other errors. An error that is not enabled sets the detect bit in this register as long as a capture has not yet occurred. You can program fields in this MSC8144E Reference Manual, Rev. 3 16-130...
Page 771 Packet Time-to-Live Error Indicates that a packet time-to-live error occurred (that is, a packet could not be successfully transmitted before the packet time-to-live counter expired). — Reserved. Write to zero for future compatibility. 1–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-131...
Page 772: Status Register
Enables reporting of a received transaction that crosses an inbound ATMU boundary. It captures and locks the error. OACB Outbound ATMU Crossed Boundary Indicates a received transaction that crosses an outbound ATMU boundary, a segment boundary, or a subsegmented boundary. MSC8144E Reference Manual, Rev. 3 16-132 Freescale Semiconductor...
Page 773 31–3 Normally, the least significant 29 bits of the address associated with the error (for requests, for responses, if available). For details, see Section 16.2.10.3, Logical Layer RapidIO Errors, on page 16-30. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-133...
Page 774 Normally, the destination ID (or least significant byte of the destination ID if large transport system) associated with the error. For details, see Section 16.2.10.3, Logical Layer RapidIO Errors, on page 16-30. MSC8144E Reference Manual, Rev. 3 16-134 Freescale Semiconductor...
Page 775 Normally, the message information: letter, mbox, and msgseg for the last message request received for the mailbox with an error (message errors only). For details, see Section 16.2.10.3, Logical Layer RapidIO Errors, on page 16-30. — Reserved. Write to zero for future compatibility. 15–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-135...
Page 776: Port 0 Error Detect Command And Status Register (P0Edcsr)
Received unaligned /SC/ or /PD/ or undefined code-group. Unsolicited Control Symbol An unsolicited acknowledge control symbol was received. Link Time-Out An acknowledge or link-response control symbol is not received within the specified time-out interval. Port MSC8144E Reference Manual, Rev. 3 16-136 Freescale Semiconductor...
Page 777: Port 0 Error Rate Enable Command And Status Register (P0Erecsr)
Unsolicited Control Symbol Enable error rate counting of unexpected acknowledge control symbols. Link Time-Out Enable error rate counting of an acknowledge or link-response control symbol not received within the specified time-out interval. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-137...
Page 778 Reserved. Write to zero for future compatibility. Error 28–24 The encoded value of the bit in the port 0 error detect CSR that describes the error captured in the port 0 error capture CSRs. MSC8144E Reference Manual, Rev. 3 16-138 Freescale Semiconductor...
Page 779 Reserved. Write to zero for future compatibility. 7–1 Contain Valid Information Hardware sets CVI to indicate that the packet/control symbol capture registers contain valid information. For control symbols, only capture register 0 contains meaningful information. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-139...
Page 780 Table 16-75. P0PCSECCSR0 Field Descriptions Reset Description Capture 0 31–0 Control character and control symbol or bytes 0–3 of the packet header. MSC8144E Reference Manual, Rev. 3 16-140 Freescale Semiconductor...
Page 781 P0ECACSR[CVI] bit is set before reading the capture registers to ensure that the error is properly captured. Table 16-76. P0PECCSR1 Field Descriptions Reset Description Capture 1 31–0 Contains bytes 4–7 of the packet header. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-141...
Page 782 P0ECACSR[CVI] bit is set before reading the capture registers to ensure that the error is properly captured. Table 16-77. PECCSR2 Field Descriptions Reset Description Capture 2 31–0 Bytes 8 to 11 of the packet header MSC8144E Reference Manual, Rev. 3 16-142 Freescale Semiconductor...
Page 783 P0ECACSR[CVI] bit is set before reading the capture registers to ensure that the error has been properly captured. Table 16-78. P0PECCSR3 Field Descriptions Reset Description Capture 3 31–0 Bytes 12–15 of the packet header. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-143...
Page 784: Port 0 Error Rate Command And Status Register (P0Ercsr)
Software should not attempt to write to ERC a value higher than the failed threshold trigger plus the number of errors specified in the ERR field (the maximum ERC value). MSC8144E Reference Manual, Rev. 3 16-144 Freescale Semiconductor...
Page 785: Port 0 Error Rate Threshold Command And Status Register (P0Ertcsr)
PnESCSR[ODE] bit is set if PnERCSR[ERC] exceeds the ERDTT value. 0x02 Set the error reporting threshold to 0xFF Set the error reporting threshold to 255. — Reserved. Write to zero for future compatibility. 15–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-145...
Page 786: Logical Layer Configuration Register (Llcr)
Blocks all maintenance requests and accesses to LCSBA1CSR. Reads return all 0s, and writes are ignored (both return a done response). When ECRAB is cleared, any external RapidIO device can access the registers. — Reserved. Write to zero for future compatibility. 28–0 MSC8144E Reference Manual, Rev. 3 16-146 Freescale Semiconductor...
Page 787: Error/Port-Write Status Register (Epwisr)
Reserved. Can be used to indicate errors on more ports if they exist. 30–2 Message Unit Logical/Transport Layer Error Interrupt Indicates a logical/transport layer error interrupt was generated by the message unit. Port Write Indicates an inbound port-write was received. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-147...
Page 788: Logical Retry Error Threshold Configuration Register (Lretcr)
Set the error reporting threshold to 1. consecutive logical retries received for a given packet that causes the RAPIDIO ENDPOINT to 0xFF Set the error reporting threshold to 255. report an error condition. MSC8144E Reference Manual, Rev. 3 16-148 Freescale Semiconductor...
Page 789: Physical Retry Error Threshold Configuration Register (Pretcr)
The threshold value for the number of consecutive 0x01 Set the error reporting acknowledge-retries received that cause the RAPIDIO threshold to 1. ENDPOINT to report an error condition. 0xFF Set the error reporting threshold to 255. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-149...
Page 790: Port 0 Alternate Device Id Command And Status Register (P0Adidcsr)
Reserved. Write to zero for future compatibility. 30–24 ADID Alternate Device ID 23–16 Alternate device ID in a small transport system. LADID Large Alternate Device ID 15–0 Alternate device ID for the device in a large transport system. MSC8144E Reference Manual, Rev. 3 16-150 Freescale Semiconductor...
Page 791: Port 0 Accept-All Configuration Register (P0Aacr)
All packets are accepted without the tt field value must be consistent with the checking the target ID. common transport system specified by the CTLS bit of the processing element features CAR. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-151...
Page 792 Time-out Value 31–8 Setting to all zeros disables the time-to-live time-out timer. This value is loaded each time the time-to-live time-out timer starts. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 16-152 Freescale Semiconductor...
Page 793: Port 0 Implementation Error Command And Status Register (P0Iecsr)
This bit is set again if another retry is received and the number of consecutive retries continues to exceed the retry error threshold. — Reserved. Write to zero for future compatibility. 30–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-153...
Page 794: Port 0 Physical Configuration Register (P0Pcr)
— Reserved. Write to zero for future compatibility. 1–0 MSC8144E Reference Manual, Rev. 3 16-154 Freescale Semiconductor...
Page 795: Port 0 Serial Link Command And Status Register (P0Slcsr)
Lane Sync Achieved for Lane 3 Write with 1 to clear — Reserved. Write to zero for future compatibility. 27–24 Lane Alignment Achieved Write with 1 to clear. — Reserved. Write to zero for future compatibility. 22–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-155...
Page 796: Port 0 Serial Link Error Injection Configuration Register (P0Sleicr)
The value of EIR × 32 determines the maximum value 19–0 of the pseudo-random delay between errors. For example, a value of 0x1 indicates a maximum delay of 32 character times. The value within this register should be right-justified. MSC8144E Reference Manual, Rev. 3 16-156 Freescale Semiconductor...
Page 797: Ip Block Revision Register 1 (Ipbrr1)
Reserved. Write to zero for future compatibility. 31–24 IPINT IP block Integration options = 0x0. 8–15 — Reserved. Write to zero for future compatibility. 16–23 IPCFG IP Block Configuration Options = 0x0. 7–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-157...
Page 798 Maintenance Transaction — Reserved. Write to zero for future compatibility. 31–30 TARGETID Target ID 29–22 Used to identify the target of the maintenance transaction. — Reserved. Write to zero for future compatibility. 21–20 MSC8144E Reference Manual, Rev. 3 16-158 Freescale Semiconductor...
Page 799: Port 0 Rapidio Outbound Window Translation Extended Address Registers X (P0Rowtearx)
Corresponds to bits 0–5 of the target ID for a large transport system. This field is valid only if the PEFCAR[CTLS] bit is set (see Section 16.6.5, Processing Element Features Capability Register (PEFCAR), on page 16-106). Bits 6–7 of the target ID are specified in the corresponding P0ROWTARx. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-159...
Page 800: Port 0 Rapidio Outbound Window Attributes Registers X (P0Rowarx)
00 One segment (normal) 23–22 Number of segments for this window. 01 Two segments (half-size Note: This field is reserved for default window 0. aliasing window) 10 Four segments (quarter-size aliasing window) 11 Reserved. MSC8144E Reference Manual, Rev. 3 16-160 Freescale Semiconductor...
Page 801 This field is read-only for default window 0. 011111 4 GB window size. 100000 8 GB window size. 100001 16 GB window size. 100010 32 GB window size. 100011 64 GB window size. 100100 Reserved 111111 Reserved. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-161...
Page 802: Port 0 Rapidio Outbound Window Base Address Registers
This corresponds to bits 4–23 of the 36-bit RapidIO base address. Note: Bit 0 is the most significant bit. MSC8144E Reference Manual, Rev. 3 16-162 Freescale Semiconductor...
Page 803: Port 0 Rapidio Outbound Window Segment 1-3 Registers
• SBTGTDID1: Bit 6 for small transport or bit 14 for large transport; reserved for 8 or 4 target subsegments. • SBTGTDID0: Bit 7 for small transport or bit 15 for large transport; reserved for 8, 4, or 2 target subsegments. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-163...
Page 804: Port 0 Rapidio Inbound Window Translation Address Registers
Target address to indicate the starting point of the inbound translated address. The translation address must be aligned on the basis of the size field. TRAD is reserved for default window 0. MSC8144E Reference Manual, Rev. 3 16-164 Freescale Semiconductor...
Page 805: Port 0 Rapidio Inbound Window Base Address Registers
This corresponds to bits 2–21 of the 34-bit RapidIO base address. Note: Bit 0 is the most significant bit. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-165...
Page 806: Port 0 Rapidio Inbound Window Attributes Registers X (P0Riwarx)
RDTYP Read Type 0000 Reserved. 19–16 Transaction type to run on the local memory if the access is a read. 0011 Reserved. 0100 Read. 0101 Reserved. 1111 Reserved. MSC8144E Reference Manual, Rev. 3 16-166 Freescale Semiconductor...
Page 807: Outbound Message X Mode Registers (Omxmr)
Outbound Message 0–1 Mode Registers Offset 0x13000 + x*0x100 — SCTL — TYPE RESET CIRQ_SIZ — QOIE QFIE — QEIE — MUTM TYPE RESET OMxMR allows software to start a message operation and to control various message operation characteristics. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-167...
Page 808 No QF interrupt is generated if this bit is cleared. If this bit is set and OMxSR[QF] is set, OMxSR[QFI] becomes set. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 16-168 Freescale Semiconductor...
Page 809: Outbound Message X Status Registers (Omxsr)
— — — EOMI TYPE W1C W1C W1C RESET OMxSR reports various message unit conditions during and after a message operation. Writing a 1 to the corresponding set bit clears the bit. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-169...
Page 810 When the last message operation in the outbound descriptor queue is finished and the QEIE bit in the Mode Register is set, this bit is set and an interrupt is generated. Otherwise, no interrupt is generated. This bit is cleared by writing a value of 1 to it. MSC8144E Reference Manual, Rev. 3 16-170 Freescale Semiconductor...
Page 811: Outbound Message X Descriptor Queue Dequeue Pointer Address
Contains the address of the first descriptor in memory to process. The descriptor must be aligned to a 32-byte boundary. For proper operation, this field should be modified only when the outbound message controller is not enabled. — Reserved. Write to zero for future compatibility. 4–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-171...
Page 812: Outbound Message X Source Address Registers (Omxsar)
The source address of the message operation. The contents are updated after every memory read operation. For proper operation, this field should be modified only when the outbound message controller is not enabled — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 16-172 Freescale Semiconductor...
Page 813: Outbound Message X Destination Port Register (Omxdpr)
Reserved. Write to zero for future compatibility. 15–2 MAILB Value for MBOX Field in MESSAGE Packet 1–0 For proper operation, this field should be modified only when the outbound message controller is not enabled MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-173...
Page 814: Outbound Message X Destination Attributes Register (Omxdatr)
Reserved. Write to zero for future compatibility. 25–24 DTGTINT Target Interface 23–20 The value of this field should always be set to RapidIO (0x0). — Reserved. Write to zero for future compatibility. 19–0 MSC8144E Reference Manual, Rev. 3 16-174 Freescale Semiconductor...
Page 815: Outbound Message X Double-Word Count Register (Omxdcr)
00 1000 0000 1024 bytes*. 01 0000 0000 2048 bytes*. 10 0000 0000 4096 bytes*. All other values yield undefined behavior. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-175...
Page 816: Outbound Message X Descriptor Queue Enqueue Pointer Address
Contains the address of the next free descriptor location. The descriptor must be aligned to a 32-byte boundary and a descriptor queue boundary. — Reserved. Write to zero for future compatibility. 4–0 MSC8144E Reference Manual, Rev. 3 16-176 Freescale Semiconductor...
Page 817: Outbound Message X Retry Error Threshold Configuration Register
1 time. this field should be modified only when the outbound message 0x02 Message segment controller is not enabled transmitted up to 2 times. 0xFF Message segment transmitted up to 255 times. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-177...
Page 818: Outbound Message X Multicast Group Registers (Omxmgr)
Outbound Message Destination Port Register (see Table 16-107, OMxDPR Field Descriptions, on page 16-173). Table 16-112. OMxMGR Field Descriptions Bits Name Description — Reserved. Write to zero for future compatibility. 31–11 MSC8144E Reference Manual, Rev. 3 16-178 Freescale Semiconductor...
Page 819: Outbound Message X Multicast List Registers (Omxmlr)
33, 65, 97, and so on. If none of the bits are set, bit 31 is assumed to be set. For proper operation, this field should be modified only when the outbound message controller is not enabled. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 820: Inbound Message X Mode Registers (Imxmr)
0100 32 bytes. controller is not enabled. 0101 64 bytes. 0110 128 bytes. 0111 256 bytes. 1000 512 bytes. 1001 1024 bytes. 1010 2048 bytes. 1011 4096 bytes. 1100– 1111 Reserved. MSC8144E Reference Manual, Rev. 3 16-180 Freescale Semiconductor...
Page 821 (IMxSR[MRT]). The busy bit (IMxSR[MB]) clears if the port response timer value (PRTOCCSR[TV]) is not set to the disabled value. If it is set to the disabled value, the busy bit does not clear. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-181...
Page 822: Inbound Message X Status Registers (Imxsr)
Set when an internal error condition occurs during the message operation. TE is cleared by writing a 1 to it. For proper operation, this bit should be modified only when the inbound message controller is not enabled. — Reserved. Write to zero for future compatibility. 6–5 MSC8144E Reference Manual, Rev. 3 16-182 Freescale Semiconductor...
Page 823 If the queue has accumulated the number of messages specified by the IMxMR[MIQ_THRESH] and the IMxMR[MIQIE] bit is set, this bit is set and an interrupt is generated. This bit is cleared by writing a 1 to it. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-183...
Page 824: Inbound Message X Frame Queue Dequeue Pointer Address Registers
Table 16-116. IMxFQDPAR Field Descriptions Bits Reset Description FQDPA Frame Dequeue Pointer Address 31–3 Contains the address of the first message in memory to process. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 16-184 Freescale Semiconductor...
Page 825: Inbound Message X Frame Queue Enqueue Pointer Address Registers
Contains the address of the next message frame to be added to the queue. For proper operation, this field should be modified only when the inbound message controller is not enabled. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-185...
Page 826: Inbound Message X Maximum Interrupt Report Interval Registers
Maximum interval between receiving the first message and setting IMxSR[IMIQ]. A value of 0 disables the time-out timer. For proper operation, this field should be modified only when the inbound message controller is not enabled. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 16-186 Freescale Semiconductor...
Page 827: Outbound Doorbell Mode Register (Odmr)
Reserved. Write to zero for future compatibility. 31–1 Doorbell Unit Start A 0-to-1 transition when the doorbell unit is not busy (ODSR[DUB] bit has a value of 0) starts the doorbell unit. A 1-to-0 transition has no effect. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-187...
Page 828: Outbound Doorbell Status Register (Odsr)
EODI is cleared by writing a 1 to it. For proper operation, this bit should be cleared only when a doorbell operation is not in progress. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 16-188 Freescale Semiconductor...
Page 829: Outbound Doorbell Destination Port Register (Oddpr)
Contains the target route field of the transaction (device ID of the target). For proper operation, this field should be modified only when a doorbell operation is not in progress. — Reserved. Write to zero for future compatibility. 15–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-189...
Page 830: Outbound Doorbell Destination Attributes Register (Oddatr)
INFO_LSB LSB of Doorbell INFO 7–0 Least significant byte of the doorbell INFO field. This field should be modified onlyy when a doorbell operation is not in progress. MSC8144E Reference Manual, Rev. 3 16-190 Freescale Semiconductor...
Page 831: Outbound Doorbell Retry Error Threshold Configuration Register
This field should be modified 0x02 Doorbell transmitted up to 2 times only when a doorbell operation is not in progress. 0xFF - Doorbell transmitted up to 255 times. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-191...
Page 832: Inbound Doorbell Mode Registers (Idmr)
For proper operation, this field should be modified only 0100 when the doorbell controller is not enabled. 0101 0110 128. 0111 256. 1000 512 (4 KB page boundary). 1001 1024. 1010 2048. 1011– 1111 Reserved. MSC8144E Reference Manual, Rev. 3 16-192 Freescale Semiconductor...
Page 833 Hardware then increments the ODQEPAR and clears this bit. DI always reads as 0. Doorbell Enable Inbound doorbell disabled. Enabled/disables the inbound doorbell operations. The inbound doorbell is initialized and can service incoming doorbell operations. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-193...
Page 834 Indicates that a doorbell has been received and the doorbell queue is being written. This bit is cleared when the write to memory finishes. Disabling the doorbell controller does not affect this bit. Read only. MSC8144E Reference Manual, Rev. 3 16-194 Freescale Semiconductor...
Page 835: Inbound Doorbell Queue Dequeue Pointer Address Register (Idqdpar)
Table 16-126. IDQDPAR Field Descriptions Bits Reset Description DQDPA Doorbell Dequeue Pointer Address 31–3 Contains the double-word address of the first doorbell in memory to process. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-195...
Page 836: Inbound Doorbell Queue Enqueue Pointer Address Registers
Contains the double-word address of the next doorbell location to be added to the queue. For proper operation, this field should be written only when the doorbell controller is disabled. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 16-196 Freescale Semiconductor...
Page 837: Inbound Doorbell Maximum Interrupt Report Interval Register
Maximum interval between the time a doorbell message goes into the queue until an interrupt is generated. A value of 0 disables the timer. This field should be written only when the doorbell controller is disabled. — Reserved. Write to zero for future compatibility. 7–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-197...
Page 838: Inbound Port-Write Mode Register (Ipwmr)
(IPWSR[QF]), clears this bit, and allows another port-write to be received. This bit is always read as a 0. Port Write Enable If this bit is set the port-write controller is initialized and can service an incoming operation. MSC8144E Reference Manual, Rev. 3 16-198 Freescale Semiconductor...
Page 839: Inbound Port-Write Status Register (Ipwsr)
A port-write has been received and the the port-write controller does not affect this bit. port-write payload is being written to memory. Read only. — Reserved. Write to zero for future compatibility. 1–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 16-199...
Page 840: Inbound Port-Write Queue Base Address Register (Ipwqbar)
Port-Write Queue Base Address 31–6 Contains the address of the port-write data payload. This field should be written only when the port-write controller is disabled — Reserved. Write to zero for future compatibility. 5–0 MSC8144E Reference Manual, Rev. 3 16-200 Freescale Semiconductor...
Page 841: Rapidio Interface Dedicated Dma Controller
RapidIO Interface Dedicated DMA Controller The MSC8144E includes a dedicated DMA controller that transfers blocks of data between the serial RapidIO controller and the local address space independent from the DSP cores. Figure 17-1 shows the block diagram of the dedicated DMA controller.
Page 842: Overview
Direct mode. No descriptors are involved. Software must initialize the required fields as described in Table 17-1 before starting a transfer. Chaining mode. Software must initialize descriptors in memory and the required fields as described in Table 17-1 before starting a transfer. MSC8144E Reference Manual, Rev. 3 17-2 Freescale Semiconductor...
Page 843 DMA operational flow chart. Software Sets 1st Link Process Link Advance Link Last Link? Chain or Extended Mode? Last List? Done — DMA Halts Advance List Figure 17-2. DMA Operational Flow Chart MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-3...
Page 844: Functional Description
This mode is primarily included for backward compatibility with existing DMA controllers which use a simple programming model. This is the default mode out of reset. The different modes of operation under the basic mode are explained in the following sections. MSC8144E Reference Manual, Rev. 3 17-4 Freescale Semiconductor...
Page 845: Basic Direct Mode
Poll the channel state (see Table 17-2), to confirm that the specific DMA channel is idle. Initialize the source attributes (SATRn), DATRn, and BCRn registers. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-5...
Page 846: Basic Chaining Mode
Basic chaining single-write start mode allows a chain to be started by writing the current link descriptor address register (CLNDARn). Setting MRn[CDSM/SWSM] in the mode register causes MRn[CS] to be automatically set when the current link descriptor address register is MSC8144E Reference Manual, Rev. 3 17-6 Freescale Semiconductor...
Page 847: Extended Dma Mode Transfer
SATRn[SSME] and setting the desired stride size and distance in SSRn. Striding on the destination address can be accomplished by setting DATRn[DSME] and setting the desired stride size and distance in DSRn. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-7...
Page 848 Initialize the current list descriptor address register to point to the first list descriptor segment in memory. This write automatically causes the DMA controller to begin the list descriptor fetch and set MRn[CS]. MSC8144E Reference Manual, Rev. 3 17-8 Freescale Semiconductor...
Page 849: Channel Continue Mode For Cascading Transfer Chains
The channel halts if NLSDARn[EOLSD] is still set. If not, the next list descriptor address is copied into the CLSDARn register and the channel continues with another descriptor fetch of the current list MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-9...
Page 850: Channel Abort
Ready to start a transfer, or transfer completed Continue transfer (only meaningful in chaining mode, not direct mode). In direct mode, the channel continue has no effect. Error occurred during transfer Channel remains in error halt state MSC8144E Reference Manual, Rev. 3 17-10 Freescale Semiconductor...
Page 851: Illustration Of Stride Size And Stride Distance
Transfer started with a byte count of zero Stride transfer started with a stride size of zero Transfer started with a priority of three Illegal type, defined by SATRn[SREADTTYPE] and DATRn[DWRITETTYPE], used for the transfer. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-11...
Page 852: Dma Descriptors
Contains the stride information used for the data source if striding is enabled for a link in the list Destination stride Contains the stride information used for the data destination if striding is enabled for a link in the list Table 17-4 summarizes the DMA link descriptors. MSC8144E Reference Manual, Rev. 3 17-12 Freescale Semiconductor...
Page 853 Next List Descriptor Address 0x08 First Link Descriptor Extended Address 0x0c First Link Descriptor Address 0x10 Source Stride 0x14 Destination Stride 0x18 Reserved 0x1c Reserved Figure 17-5. List Descriptor Format (Used for 36-bit devices) MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-13...
Page 854: Local Access Atmu Registers
Note: See Section 17.3.1, Local Access Window Base Address Registers 0–9 (LAWBAR[0–9]), on page 17-17 and Section 17.3.2, Local Access Window Attributes Registers 0–9 (LAWAR[0–9]), on page 17-18 for details. MSC8144E Reference Manual, Rev. 3 17-14 Freescale Semiconductor...
Page 855: Limitations And Restrictions
0x11). Software is responsible for disabling striding and DAHE, in this case, and for ensuring that the bandwidth control is large enough to support the desired message size. Failure to adhere to these restrictions results in undefined behavior. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-15...
Page 856: Dedicated Dma Controller Programming Model
DMA 0–3 Source Stride Registers (SSR[0–3]), page 17-40 DMA 0–3 Destination Stride Registers (DSR[0–3]), page 17-41 DMA General Status Register (DGSR), page 17-42 Note: The dedicated DMA registers use a base address of 0xFFFA2000. MSC8144E Reference Manual, Rev. 3 17-16 Freescale Semiconductor...
Page 857: Local Access Window Base Address Registers 0–9 (Lawbar[0–9])
Reserved. Write to zero for future compatibility. 31–24 Base Address 23–0 Holds the 24 most significant bits of the window base address. Note: For local transactions, the most significant 4 bits in this field must be 0s. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-17...
Page 858: Local Access Window Attributes Registers 0–9 (Lawar[0–9])
Specifies the logical destination/target of the 1111 Local address space. transaction mapped to this window. A reserved All others reserved. value defaults to local address space. — Reserved. Write to zero for future compatibility. 19–6 MSC8144E Reference Manual, Rev. 3 17-18 Freescale Semiconductor...
Page 859 001110 64G. 001111 010000 128K 010001 256K 010010 512K 010011 010100 010101 010110 010111 011000 011001 011010 128M 011011 256M 011100 512M 011101 011110 011111 100000 100001 100010 100011 All others reserved. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-19...
Page 860: Mode Registers 0–3 (Mr[0–3])
11 8 bytes. based on the size. The defined size must be equal to or small than the value of MR[BWC] to avoid undefined behavior. MSC8144E Reference Manual, Rev. 3 17-20 Freescale Semiconductor...
Page 861 Extended Chaining Enable (CTM = 0 only) Extended chaining disabled. When set, enables extended chaining mode. Extended chaining enabled. Note: This bit is reserved in direct mode. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-21...
Page 862 Starts the DMA process if the channel is idle (SR[CB] is cleared). Setting the bit while the channel is busy continues the current transfer from the point at which it stopped. MSC8144E Reference Manual, Rev. 3 17-22 Freescale Semiconductor...
Page 863: Status Registers (Srn)
Write a 1 to this bit to clear it. Channel Busy Channel is idle, DMA transfer Indicates the current status of the channel. completed, error occurred, or a channel abort occurred. DMA transfer is in progress. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-23...
Page 864 After transferring the last block of data in the last list End-of-list interrupt. descriptor, if MR[EOLSIE] is set, then this bit is set and an interrupt is generated. Note: Write a 1 to this bit to clear it. MSC8144E Reference Manual, Rev. 3 17-24 Freescale Semiconductor...
Page 865: Current Link Descriptor Extended Address Registers (Eclndarn)
31–4 ECLNDA Current Link Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-25...
Page 866: Current Link Descriptor Address Registers (Clndarn)
Enables/disables the end-of-segment interrupt at interrupt. the completion of the current DMA transfer for the Generate end-of-segment interrupt current link descriptor. when transfer is complete. — Reserved. Write to zero for future compatibility. 2–0 MSC8144E Reference Manual, Rev. 3 17-26 Freescale Semiconductor...
Page 867: Source Attributes Registers (Satrn)
Bypass ATMU. Never generate an address match. Always use the SATR values to route the transaction to the interface specified by the STRANSMIT field. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-27...
Page 868 • RapidIO interface: Bits 9–2 represent the target ID and bits 1–0 represent the two most significant bits of the RapidIO address (33–32). Note: This field must be cleared (0) in non-bypass mode. MSC8144E Reference Manual, Rev. 3 17-28 Freescale Semiconductor...
Page 869: Source Address Registers (Sarn)
This value is defined by the RapidIO Interconnect Specification 1.2. CONFIG_ Maintenance Packet Word Offset OFFSET This value is defined by the RapidIO Interconnect Specification 1.2. Bits 1–0 are always zero 23–-0 because the value is 4-byte aligned. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-29...
Page 870: Destination Attributes Registers (Datrn)
Bypass ATMU. Never generate an address match. Always use the SATR values to route the transaction to the interface specified by the DTRANSMIT field. — Reserved. Write to zero for future compatibility. MSC8144E Reference Manual, Rev. 3 17-30 Freescale Semiconductor...
Page 871 • RapidIO interface: Bits 9–2 represent the target ID and bits 1–0 represent the two most significant bits of the RapidIO address (33–32). Note: This field must be cleared (0) in non-bypass mode. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-31...
Page 872: Destination Address Registers (Darn)
This value is defined by the RapidIO Interconnect Specification 1.2. CONFIG_ Maintenance Packet Word Offset OFFSET This value is defined by the RapidIO Interconnect Specification 1.2. Bits 1–0 are always zero 23–-0 because the value is 4-byte aligned. MSC8144E Reference Manual, Rev. 3 17-32 Freescale Semiconductor...
Page 873: Byte Count Registers (Bcrn)
31–26 Byte Count 25–0 Contains the number of bytes to transfer. The value in this field is decremented after each DMA read operation. The maximum transfer size is 2 – 1 bytes. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-33...
Page 874: Extended Next Link Descriptor Address Registers (Enlndarn)
31–4 ENLNDA Next Link Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8144E Reference Manual, Rev. 3 17-34 Freescale Semiconductor...
Page 875: Next Link Descriptor Address Registers (Nlndarn)
Enables/disables the next descriptor Generate next descriptor end-of-segment interrupt when the current DMA end-of-segment interrupt when transfer for the current link descriptor completes. transfer is complete. — Reserved. Write to zero for future compatibility. 2–1 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-35...
Page 876: Extended Current List Descriptor Address Registers (Eclsdarn)
31–4 ECLSDA Current List Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8144E Reference Manual, Rev. 3 17-36 Freescale Semiconductor...
Page 877: Current List Descriptor Address Registers (Clsdarn)
RapidIO transactions, it is the lower portion of the 36-bit address formed by combining with the ECLSDA for use with RapidIO transaction types. — Reserved. Write to zero for future compatibility. 4–0 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-37...
Page 878: Extended Next List Descriptor Address Registers (Enlsdarn)
31–4 ENLSDA Next List Descriptor Extended Address 3–0 Contains the most significant 4 bits of the 36-bit address used with RapidIO transactions only. Note: This field is not used for local transactions. MSC8144E Reference Manual, Rev. 3 17-38 Freescale Semiconductor...
Page 879: Next List Descriptor Address Registers (Nlsdarn)
Last list descriptor in memory. descriptor in memory. When the bit is set, the DMA controller halts after the last link descriptor transaction finishes. Note: This bit is ignored in direct mode. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-39...
Page 880: Source Stride Registers (Ssrn)
Holds the number of bytes to transfer before jumping to the next address as specified in the source stride distance field. Source Stride Distance 11–0 The source stride distance in bytes from the start byte to the end byte. MSC8144E Reference Manual, Rev. 3 17-40 Freescale Semiconductor...
Page 881: Destination Stride Registers (Dsrn)
Holds the number of bytes to transfer before jumping to the next address as specified in the destination stride distance field. Destination Stride Distance 11–0 The destination stride distance in bytes from the start byte to the end byte. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-41...
Page 882: Dma General Status Register (Dgsr))
Channel 1 Programming Error Detected Normal operation. Indicates whether a programming error was Programming error detected. detected. EOLNI1 Channel 1 End-of-Links Interrupt Normal operation. Indicates whether an end-of-links interrupt End-of-links interrupt occurred. occurred. MSC8144E Reference Manual, Rev. 3 17-42 Freescale Semiconductor...
Page 883 Channel 3 End-of-Segment Interrupt Normal operation. Indicates whether an end-of-segment interrupt End-of-segment interrupt occurred. occurred. EOLSI3 Channel 3 End-of-Lists/Direct Interrupt Normal operation. Indicates whether an end-of lists/direct interrupt End-of-list/direct interrupt occurred. occurred. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 17-43...
Page 884 RapidIO Interface Dedicated DMA Controller MSC8144E Reference Manual, Rev. 3 17-44 Freescale Semiconductor...
Page 885 This allows the cores to execute the data processing code and be relieved from the data transfer and handling overhead. This chapter provides an overview of the QUICC Engine subsystem components used in the MSC8144E, which include the following: Dual RISC engines with —...
Page 886: Overview
Instruction Peripheral Bus UCC1 UCC3 UCC5 SPI1 Communication Interfaces MII/RMII/SMII RMII/SMII UL8/16/POS RGMII RGMII MIIGSK MIIGSK SerDes SerDes MII/RMII/SMII RMII/SMII SGMII SGMII RGMII RGMII Figure 18-1. QUICC Engine Subsystem Architectural Block Diagram MSC8144E Reference Manual, Rev. 3 18-2 Freescale Semiconductor...
Page 887: Risc Processors
The RISC processor generates interrupts through the interrupt controller. The SC3400 cores can read the QUICC Engine subsystem status/event registers at any time. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-3...
Page 888: Peripheral Interface
Table 18-1. Default Parameter RAM Base Addresses Size Address Offset Peripheral (Bytes) 0x8400 UCC 1 (Rx and Tx) 0x8600 UCC 3 (Rx and Tx) 0x8000 UCC 5 (Rx and Tx) 0x8900 SPI (Rx and Tx) MSC8144E Reference Manual, Rev. 3 18-4 Freescale Semiconductor...
Page 889: Buffer Descriptors (Bds)
Refer to the relevant chapter in this manual for each protocol RxBD.bd_cstat bit description. TxBD.bd_cstat Data length. The 16-bit value at , which contains the number of bytes sent or offset+0x2 received. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-5...
Page 890: Multithreading
RAM located in the multi-port RAM. The user software initializes the values for the SNUM and the pointer of the parameter RAM base address at initialization time. Note: See the QUICC Engine™ Block Reference Manual with Protocol Interworking (QEIWRM).for specific interface configuration details. MSC8144E Reference Manual, Rev. 3 18-6 Freescale Semiconductor...
Page 891: Serial Numbers (Snums)
Reserved 0x7D — 0xBD — 0xFD — Note: See the QUICC Engine™ Block Reference Manual with Protocol Interworking (QEIWRM) for details on how to use the SNUM with the ASSIGN PAGE command. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-7...
Page 892: Iram
18.3.1 Data Paths Figure 18-4 is a simplified block diagram that shows the data paths in the MSC8144E. The MSC8144E may be implemented with one DDR bus (32 or 64 bit data). SerDes Interface...
Page 893: Sdma And Bus Error
Engine subsystem. For debug purposes, it is valuable to observe continued operation, but a selective recovery does not provide any added value. This non-distinctive procedure also reduces the complexity of the recovery flow. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-9...
Page 894: Selective Peripheral Recovery Procedure
SDTR/SDHY registers). A priority request to the multi-user RAM is also asserted by the SDMA, if needed, for the same reasons. It is possible to mask the high priority request globally in SDMR[ERMSK]. MSC8144E Reference Manual, Rev. 3 18-10 Freescale Semiconductor...
Page 895: Sdma Internal Resource
(BRG[5–8]) and a bank of external clocks. Physical signal connections are also configured using the clock route registers. However, because these signal lines are multiplexed with other functions at the I/O lines, you must make sure that MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-11...
Page 896 There are two main advantages to the bank-of-clocks approach. First, a peripheral is not forced to choose a serial device clock from a predefined input or BRG. Second, peripheral receivers and transmitters that need the same clock rate can share the same source. This MSC8144E Reference Manual, Rev. 3 18-12 Freescale Semiconductor...
Page 897 Table 18-4. Clock Source Options Using External Clock Signals External CLK Clock GE1_RX_CLK GE1_TX_CLK GE2_RX_ER GE2_RX_CLK UTP_RCLK UTP_TCLK UTP_IR UCC1 Rx UCC1 Tx UCC3 Rx UCC3 Tx UPC Rx UPC Tx UPC internal rate Time Stamp 1 Time Stamp 2 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-13...
Page 898 Table 18-5. Clock Source Options - Internal Clock Generators BRG Number Clock UCC1 Rx UCC1 Tx UCC3 Rx UCC3 Tx UPC Rx UPC Tx UPC internal rate is the UPC1 Tx clock MSC8144E Reference Manual, Rev. 3 18-14 Freescale Semiconductor...
Page 899: Baud-Rate Generators (Brgs)
The QUICC Engine subsystem interrupt controller sends general interrupts to the DSP cores in the MSC8144E device. The core must then initiate the correct interrupt service routine to handle the interrupt. Typically, this routine must read the interrupt status registers in the QUICC Engine subsystem to determine the appropriate action to take.
Page 900: Quicc Engine Subsystem List Of Interrupts To Core
Category Interrupt Global Interrupts QUICC Engine subsystem DRAM ECC ERROR QUICC Engine subsystem IMEM ECC ERROR QUICC Engine subsystem Interrupt High QUICC Engine subsystem Interrupt Low UCC1 SMII Interrupt UCC3 SMII Interrupt MSC8144E Reference Manual, Rev. 3 18-16 Freescale Semiconductor...
Page 901 Global interrupt 0 Global interrupt 1 Global interrupt 2 Global interrupt 3 Global red-line Interrupt queue 0 overflow Interrupt queue 1 overflow Interrupt queue 2 overflow Interrupt queue 3 overflow Transmit internal rate underrun MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-17...
Page 902: Interrupt Configuration
ATM dedicated interrupts. For more details about these dedicated interrupts see UCCE and UCCM of each protocol. Note: See the QUICC Engine™ Block Reference Manual with Protocol Interworking (QEIWRM) for details about configuring the QUICC Engine interrupt system. MSC8144E Reference Manual, Rev. 3 18-18 Freescale Semiconductor...
Page 903: Uccs
The FIFO as shown in Figure 18-9 is constructed using a real hardware FIFO embedded in the UCC and its extension to a virtual FIFOs in the QUICC Engine MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor...
Page 904: Ethernet Controllers
LAN, this manual uses the generic term Ethernet unless otherwise noted. The MSC8144E uses two UCC Gigabit Ethernet Controllers (UECs) coordinated through the QUICC Engine subsystem. Each controller supports several standard MAC-PHY interfaces to connect to an external Ethernet transceiver.
Page 905 Serial-GMH Specification defines a serial gigabit interface for Ethernet. The specification is available from the Cisco website at: ftp://ftp-eng.cisco.com/smii/sgmii.pdf The MSC8144E implements the SGMII through a SerDes interface shared with the Serial ® RapidIO signals. Refer to Chapter 16, Serial RapidIO Controller for details on this shared interface.
Page 906 10/100 Mbps MII interface (IEEE 802.3-2002 standard) 1000 Mbps RGMII interface. 10/100 RMII interface. 10/100 SMII interface. The SMII interface is supported by the MIIGSK.The MIIGSK controller also supports a SYNC_IN signal. 1000 Mbps SGMII interface. MSC8144E Reference Manual, Rev. 3 18-22 Freescale Semiconductor...
Page 907: Operating Modes
In order to accomplish this objective, the data paths and all associated control signals are reduced and control signals are multiplexed together and both edges of the clock are used. For Gigabit operation, the clocks operate at 125 MHz. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-23...
Page 908: Sgmii Mode
Note: The MSC8144E allows adjustment of the transmission delays for the Ethernet signal lines (except SGMII) using GCR4. Recommended settings are listed in the MSC8144E data sheet. Guidelines for adjusting these numbers in individual designs is provided in Using GCR4 to Adjust Ethernet Timing in MSC8144 DSPs (AN3811), available at www.freescale.com.
Page 909 RMII. Transmit data bits 0–2. Output SMII. Transmit data bit 0. Output SMII. SYNC on TXD[1] Output RGMII. Rising edge (transmit data bits 0–3). Output RGMII. Falling edge (transmit data bit 4–7). Output MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-25...
Page 910 RMII. Transmit data enable. Output RGMII. Rising edge (transmit data enable). Output RGMII. Falling edge (transmit error). Output RGMII. SMII. Not used. — TX_ER MII. Transmit error Output RMII, RGMII, SMII. Not used. — MSC8144E Reference Manual, Rev. 3 18-26 Freescale Semiconductor...
Page 911: Media-Independent Interface (Mii)
TX_ER TX_EN UCC1 Ethernet MAC TXD[0–3] TX_CLK MII Mode Physical MDIO RX_ER RX_DV RXD[0–3] RX_CLK MAC Layer Note: Signal names are according to 802.3 standard (total:16 ports). Figure 18-11. MII MAC-PHY Interface MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-27...
Page 912 MII. It remains asserted for the remainder of the frame, up to the last CRC byte RXD[0–3] Receive Data RX_CLK RX_CLK Receive Clock — Synchronizes all receive signals (RX_DV, RXD, RX_ER). MSC8144E Reference Manual, Rev. 3 18-28 Freescale Semiconductor...
Page 913: Reduced Media-Independent Interface (Rmii) Signals
RMII Physical CRS_DV Receiver REF_CLK RX_ER Conversion RX_DV RX_ER RXD[0–3] RXD[0–1] RX_CLK MAC Layer Note: Signals names are according to the IEEE 802.3 standard (total: 8 ports). Figure 18-12. RMII MAC-PHY Interface MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-29...
Page 914: Smii Interface
ETHSYNC_IN input by writing a 1 to MIIGSK_SMII_SYNCDIR[SYNC_IN] and a 0 to MIIGSK_SMII_DYNCDIR[SYNC]. The operating mode is determined by the Frequency Control bit (MIIGSK_CFGR[FRCONT]); the default value 0 selects 100 Mbps operation. MSC8144E Reference Manual, Rev. 3 18-30 Freescale Semiconductor...
Page 915: Reduced Gigabit Media-Independent Interface (Rgmii) Signals
(GMII) to 13 pins (GTX_CLK included). The data paths and all associated control signals are reduced, control signals are multiplexed, and both edges of the clock are used. Figure 18-15 shows the RGMII connections between the Ethernet controller and a PHY. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-31...
Page 916 RX_ER on clock negative edge. Rx Data Receive Data RXD[0–3] on clock posedge RXD[4–7] on clock negedge MDIO Management Data I/O Transfers control signals between the PHY layer and the manager entity. MSC8144E Reference Manual, Rev. 3 18-32 Freescale Semiconductor...
Page 917: Serial Gigabit Media-Independent Interface (Sgmii) Signals
Differential pair for Ethernet 2 controller. SRIO_REF_CLK SG2_RX MDIO Management Data I/O Transfers control signals between the PHY layer and the manager entity. Management Data Clock — The MDIO signal clock reference (25 MHz clock). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-33...
Page 918: Controlling Phy Links (Management Interface)
UTFET, UTFTT, URTRY UCC event register, Fast UCCE Initialize interrupts to prepare for interrupt events UCC mask register, Fast UCCM Initialize the interrupt mask to prepare for interrupt events Activate The Ethernet Controller MSC8144E Reference Manual, Rev. 3 18-34 Freescale Semiconductor...
Page 919: Asynchronous Transfer Mode (Atm) Controller
18.8 Asynchronous Transfer Mode (ATM) Controller The MSC8144E uses UCC5 to support one ATM controller managed through the QUICC Engine subsystem. UCC5 manages the data flow internally through its receive and transmit FIFOs. The QUICC Engine subsystem performs frame control and manipulation using firmware executed by the RISC engines according to the specified protocol requirements.
Page 920 ATM Layer, it must reassemble the payloads into a format the higher layers can understand. This operation, which is called Segmentation and Reassembly (SAR), is the main task of AAL. Different AALs are defined to support different traffic or services. MSC8144E Reference Manual, Rev. 3 18-36 Freescale Semiconductor...
Page 921: Atm Controller Architecture
8-bit mode and 52 bits in 16-bit mode. Table 18-13 summarizes all possible I/O pins assignments combinations. Table 18-13. UCC UTOPIA/POS I/O Pin Count UTOPIA 31 PHYs POS 31 PHYs 8 bit Data 16 bit Data parity Address Clav/xPTA Clock MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-37...
Page 922: Utopia Interface Master Mode
UTOPIA device configuration requires a total of 36 I/O ports for 8-bit mode and 52 bits in 16-bit mode. Both configuration use the same number of control signals; only the data signal lines are different. UTOPIA slave signals are shown in <Cross Refs>Figure 18-18. MSC8144E Reference Manual, Rev. 3 18-38 Freescale Semiconductor...
Page 923: Pos Interface Master Mode
(UPC Rx) TERR RERR RENB0 TENB0 RVAL STPA PRPA/DRPA0 PTPA0/DTPA0 RPRTY TPRTY RFCLK TFCLK RADD[4–0] TADD[4–0] Figure 18-19. POS Master Mode Signals , External Signals See Chapter 3 for detailed signal descriptions. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-39...
Page 924: Pos Interface Slave Mode
When the SPI is disabled in the SPI mode register (SPMODE[EN] = 0), it consumes little power. The SPI operates in QUICC Engine mode. In QUICC Engine mode SPI, which is compatible to the MPC826x SPI, and is controlled by QUICC Engine RISC. MSC8144E Reference Manual, Rev. 3 18-40 Freescale Semiconductor...
Page 925: Spi Operating Modes
I/O signals to selectively enable slaves, as shown in Figure 18-22. To eliminate the multi-master error in a single-master environment, the master SPI_SL input can be forced inactive by selecting SPI_SL for general-purpose I/O. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-41...
Page 926 If the current TxBD[L] is set, sending stops after the current buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer is not full; therefore, Rx buffers need not be the same length as Tx buffers. MSC8144E Reference Manual, Rev. 3 18-42 Freescale Semiconductor...
Page 927: Spi As A Slave Device
SPI can transfer a single character at much higher rates—QUICC Engine clk/8 in master mode and QUICC Engine clk/4 in slave mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum sustained data rate. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-43...
Page 928 • It is the responsibility of the software to arbitrate for the SPI bus (with token passing, for example). • SPI_SLx signals are implemented in the software with general-purpose I/O signals. Figure 18-23. Multimaster Configuration MSC8144E Reference Manual, Rev. 3 18-44 Freescale Semiconductor...
Page 929: External Signal Configuration
(SPIE) not-empty bit (SPIE[NE]) is set. The core processor transmits data by writing it into the SPITD. When the next character to transmit is the final one in the current MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 18-45...
Page 930: Programming Model
The core processor then reads the SPIE and acts accordingly. There are three basic modes of operation for transmitting and receiving: master, slave, and multimaster. 18.10 Programming Model This section provides a summary list of the MSC8144E QUICC Engine subsystem, Ethernet controller, ATM, and SPI registers with their offsets. Note: The QUICC Engine registers use a base address of 0xFEE00000.
Page 931 Programming Model Table 18-14. MSC8144E QUICC Engine Register Summary (Continued) Register Name Acronym Offset CECDR 0x0108 QUICC Engine Command Data Register QUICC Engine Time-Stamp Control Register CETSCR 0x011C CEVTER 0x0130 QUICC Engine Virtual Tasks Event Register QUICC Engine Virtual Tasks Mask Register...
Page 932 QUICC Engine™ Subsystem Table 18-14. MSC8144E QUICC Engine Register Summary (Continued) Register Name Acronym Offset UCC1 Transmit FIFO Transmit Threshold UTFTT1. 0x2038 UCC1 Transmit Polling Timer UFPT1 0x203C UCC1 Retry Counter URTRY1. 0x2040 UCC1 General Extended Mode Register GUEMR1. 0x2090...
Page 933 Programming Model Table 18-14. MSC8144E QUICC Engine Register Summary (Continued) Register Name Acronym Offset UCC3 General Mode Register GUMR3. 0x2200 UCC3 Protocol-Specific Mode Register UPSMR3. 0x2204 UCC3 Transmit On Demand Register UTODR3. 0x2208 UCC3 Event Register UCCE3. 0x2210 UCC3 Mask Register UCCM3.
Page 934 QUICC Engine™ Subsystem Table 18-14. MSC8144E QUICC Engine Register Summary (Continued) Register Name Acronym Offset Ethernet 2 Rx 65- to 127-byte Frames E2RX127 0x2390 Ethernet 2 Rx 128- to 255-byte Frames E2RX255 0x2394 Ethernet 2 Octet Transmitted OK E2TXOK 0x2398...
Page 935 Programming Model Table 18-14. MSC8144E QUICC Engine Register Summary (Continued) Register Name Acronym Offset UCC 5 Receive FIFO Special Emergency Threshold URFSET5 0x242A UCC 5 Transmit FIFO Base UTFB5 0x242C UCC 5 Transmit FIFO Size UTFS5 0x2430 UCC 5 Transmit FIFO Emergency Threshold...
Page 936 QUICC Engine™ Subsystem Table 18-14. MSC8144E QUICC Engine Register Summary (Continued) Register Name Acronym Offset Device 1 Transmit Internal Rate 4 UPTIRR1_4 0x2E86 Device 1 Port Enable Register UPER1 0x2EA0 SDMA Registers Serial DMA Status Register SDSR 0x4000 Serial DMA Mode Register...
Page 937 TDM Interface The MSC8144E Time-Division Multiplexing (TDM) interface enables communication among many devices over a single bus. Traffic is managed according to a time-division multiplexing method in which only one device drives the bus (transmit) for each channel. Each device drives its active transmit channels and samples its active receive channels when its channel is active.
Page 938 The eight TDM modules have an I/O matrix that routes the clock and sync signals between the TDM modules and the MSC8144E signal lines. The TDM may be configured by all four SC3400 cores (see Figure 19-1), as well as by an external host. Data is received and transmitted from the TDM modules to the channel buffers through the internal MBus.
Page 939 Rx error int7, Rx threshold1 int7, Rx threshold2 int7 Tx error int1, Tx threshold1 int1, Tx threshold2 int1 Tx error int7, Tx threshold1 int7, Tx threshold2 int7 Figure 19-1. General TDM Module Interface MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-3...
Page 940 Configuration Registers Conversion IP logic TDM DMA To internal MBus Interface To IPBus Multiplex Notes: X is the TDM number (0–7). Receive data flow: Transmit data flow: Figure 19-2. TDM Block Diagram MSC8144E Reference Manual, Rev. 3 19-4 Freescale Semiconductor...
Page 941: Typical Configurations
Typical Configurations 19.1 Typical Configurations The TDM connects in various configurations. Figure 19-3 shows two MSC8144E devices that connect point-to-point. Data transmits from the device on the left to the device on the right or vice versa. On-Board Clock Generator...
Page 942: Tdm Basics
Figure 19-5 depicts an application in which all the TDM modules share the sync and the clock (see Figure 19-11). Therefore, each TDM module supports one or two active links. In this example, 16 receive link and 16 transmit links connect to two MSC8144E devices. FSYN...
Page 943 RNCF[7–0] = 0x17 (24 channels), RCS = 0x7 (8 bits) and RT1 = 1 (T1 mode). Transmit Frame parameters: TNCF[7–0] = 0x23 (24 channels), TCS = 0x7 (8 bits) and TT1 = 1 (T1 mode) Figure 19-7. T1 Frame MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-7...
Page 944: Common Signals For The Tdm Modules
TDM0 and TDM1. When the CTS bit of the TDMx General Interface Register (see page 19-36) is cleared, the TDM modules do not share signals. In Figure 19-8, TDM2 - TDM7 do not share signals with the other TDM modules MSC8144E Reference Manual, Rev. 3 19-8 Freescale Semiconductor...
Page 945 RTSAL[3–0] = 0001 RTSAL[3–0] = 0001 RTSAL[3–0] = 0001 CTS = 1 CTS = 1 CTS = 1 CTS = 1 Figure 19-9. Shared Receive Sync and Clock and Transmit Sync and Clock MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-9...
Page 946: Receiver And Transmitter Independent Or Shared Operation
), and the data signals. In FSYN FCLK this mode, the data links are full duplex and are used for both transmit and receive, so the number of active links can be 1, 2, or 4. MSC8144E Reference Manual, Rev. 3 19-10 Freescale Semiconductor...
Page 947 Channel 2 X The TDM number. N The number of channel in the receive TDM frame. M The number of channels in the transmit TDM frame. Figure 19-12. Receive and Transmit Totally Independent MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-11...
Page 948 N Number of channels in a TDM frame. The data links are bidirectional. The clock and the sync are common. Figure 19-14. Receive and Transmit Share Sync, Clock, and Data (Four Active Links) MSC8144E Reference Manual, Rev. 3 19-12 Freescale Semiconductor...
Page 949: Tdm Data Structures
RNB field of the TDMx Receive Number of Buffers Register (TDMxRNB) (discussed on page 19-68). Channel C in buffer B is the 8 bytes starting at (256 / (RNB + 1) × B + C) × 8. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-13...
Page 950 0x89ABCDEF to address 0x1804 (offset from TDMx Receive Local Memory). If TDMxTIR[TBOR] = 1, the 0x89ABCDEF data is transmitted before the 0x01234567 data. 8 Bytes 0x1800 Figure 19-16. TDMx Local Memory Write Example MSC8144E Reference Manual, Rev. 3 19-14 Freescale Semiconductor...
Page 951: Serial Interface
The transmit frame length is determined by TDMxTFP[TT1], page 19-51 the transmitter configuration fields TCS,TNCF, TT1 and RTSAL[1–0]. TDMxGIR[RTSAL], page 19-36 The distance is = (TCS + 1) × (TNCF + 1) / (RTSAL[1–0] + 1) + TT1. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-15...
Page 952: Sync In Configuration
Therefore, the transmit delay when the transmit sync and transmit data are sampled/driven out at the same clock edge is (TFSD – 1). And when the sync and the data sampled/driven out at different clock edge is (TFSD – 1 + 0.5). MSC8144E Reference Manual, Rev. 3 19-16 Freescale Semiconductor...
Page 953 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 Channel number Channel 0 Channel 1 Channel 2 data drive Start of the frame 0 bit delay sync sample Figure 19-19. Frame Sync Configurations MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-17...
Page 954: Serial Interface Synchronization
TDM frame is identified by a frame sync signal that is asserted at the beginning of every frame. The frame sync synchronization is necessary when more than one device drives the bus. Figure 19-22 shows the state diagram of the frame sync synchronization. MSC8144E Reference Manual, Rev. 3 19-18 Freescale Semiconductor...
Page 955 Sync event found not at the expected position Sync event found at Last bit of the frame the expected position PRESYNC Figure 19-22. Frame Sync Synchronization State Diagram MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-19...
Page 956: Reverse Data Order
If TDMxRIR[RRDO] is clear, the first bit of the received channel data is stored as the most significant bit. The TDMxTIR[TRDO] bit selects the transmit data bits order. If TDMxTIR[TRDO] is clear, the most significant bit of the memory is transmitted as the first transmit data. MSC8144E Reference Manual, Rev. 3 19-20 Freescale Semiconductor...
Page 957 TDMxDAT (receive/transmit) Channel N (Channel N) Row in Memory Reverse Data Bit Order: RRDO/TRDO = 0 TDMxCLK (receive/transmit) TDMxDAT (receive/transmit) Channel N (Channel N) Row in Memory Figure 19-23. Reserve Bit Order MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-21...
Page 958: Tdm Local Memory
(only 64 bits are stored in the TDM local memory). For example, the minimum latency for a T1 application with 8 bits per channel and a frame length of 125 μs is equal to 1 ms. T1 minimum latency= 64/8 × 125 μs. MSC8144E Reference Manual, Rev. 3 19-22 Freescale Semiconductor...
Page 959: Buffers Mapped On System Memory
#4 smp #5 smp #6 smp #7 smp #8 smp #9 smp #A smp #B smp #C smp #D smp #E smp #F Figure 19-24. Receive/Transmit Main Data Buffer For A-Law/μ-Law Channel MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-23...
Page 960: Data Buffer Address
The TDBD can be used to show which data is already read from the buffer so that the buffer can be filled with new data. Note: For A/μ-law channels the RDBD and the TDBD fields should be doubled before use. MSC8144E Reference Manual, Rev. 3 19-24 Freescale Semiconductor...
Page 961 (A/μ law active) RGBA TGBA RGBA TGBA RCDBA 0000 RCPRx TCDBA 0000 TCPRx Receive data buffer i base address Transmit data buffer i base address Figure 19-25. Data Buffer Location in Main Memory MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-25...
Page 962: Threshold Pointers And Interrupts
TDMxTIR[TSTL] bit. If the interrupt is level, the ISR should clear the TDMxTER[TSTE] bit by writing a 1 to it. If the interrupt is pulse, then there is no need to clear MSC8144E Reference Manual, Rev. 3 19-26...
Page 963 The interrupt routine that handles the receive second threshold interrupt should include: If (TDMxRDBST[RDBST] == (TDMxRDBS[RDBS] - 0xF)) then TDMxRDBST[RDBST] = 0x0 else if (TDMxRDBST[RDBST] == (TDMxRDBS[RDBS] - 0x7)) then TDMxRDBST[RDBST] = 0x8 else TDMxRDBST[RDBST] = TDMxRDBST[RDBST] + 0x10 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-27...
Page 964: Unified Buffer Mode
Channel 0 is a transparent channel. TCPR1[TCDBA] Channel 1 is a transparent channel Transmit Data Buffer TDBS RCPR1[RCONV]=00. Channel k is an A/μ law channel RCPRk[RCONV]=10. Figure 19-27. Transmit Data Buffer in Independent Data Buffer Mode (TUBM=0) MSC8144E Reference Manual, Rev. 3 19-28 Freescale Semiconductor...
Page 965: Adaptation Machine
Mode, the TRDO bit in the TDMxTIR should be cleared. 19.2.7 Adaptation Machine Each TDM module has an Adaptation Machine that counts the number of bits between frame SYNCs. This module can be used to determine the frame size in bits. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-29...
Page 966 Read the value of the ASD field in the TDMxASDR. (See the TDMxASDR indicates the number of receive/transmit bits between the last two consecutive receive/transmit sync events. The register value updates each time the TDMxASR[AMS] bit is set. on page 19-71). MSC8144E Reference Manual, Rev. 3 19-30 Freescale Semiconductor...
Page 967: Tdm Power Saving
— SYN 19.3 TDM Power Saving The MSC8144E TDMs use the stop mode of different clocks to save power. Each TDM has three clock domains: transmit serial, receive serial, and the CLASS64 clock. The transmit serial clock is not supplied to the TDM module when the transmitter is disabled, that is, the TDMxTCR[TEN] bit and the TDMxTSR[TENS] are both clear.
Page 968: Loopback Support
(TFSE) bits to 1. The sync samples at the negative edge. — The value of the Receive Sync level bit should be identical to that of the Transmit Sync Level field (RSL = TSL). MSC8144E Reference Manual, Rev. 3 19-32 Freescale Semiconductor...
Page 969: Tdm Initialization
Perform a hardware reset to disable the receiver and the transmitter. Program all the configuration registers. Program all the control registers, except the TDMx Receive Control Register (TDMxRCR) and the TDMx Transmit Control Register (TDMxTCR). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-33...
Page 970: Tdm Programming Model
Control registers. Set the channel specific parameters individually for each channel and the threshold pointers. These registers can be changed during operation. Status registers. Read-only registers that can be accessed any time. MSC8144E Reference Manual, Rev. 3 19-34 Freescale Semiconductor...
Page 971 TDMx Transmit Event Register (TDMxTER), page 19-70. TDMx Adaptation Status Register (TDMxASR), page 19-71. TDMx Receive Status Register (TDMxRSR), page 19-72. TDMx Transmit Status Register (TDMxTSR), page 19-73. TDMx Parity Error Register (TDMxPER), page 19-73. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-35...
Page 972: Configuration Registers
Sync Mode Non-sync mode. Used to synchronize the start of each TDM receiver/transmitter with Sync mode. enabling the TDM0 transmitter. In this mode, the TDM0 transmitter should be the last to operate. MSC8144E Reference Manual, Rev. 3 19-36 Freescale Semiconductor...
Page 973 RTSAL field. Note: If the TDM modules share sync and clock signals, then the RFP, TFP,RIR, and TIR registers should be configured the same way for all the TDM modules. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-37...
Page 974 1110 Reserved. 1111 The receive and transmit share the frame sync, frame clock, and four full duplex data links. Refer to Table 19-8 MSC8144E Reference Manual, Rev. 3 19-38 Freescale Semiconductor...
Page 975 TDMy specifies the TDM number and any one of the shared TDM modules except of TDM0. for example if TDM0 and TDM1 shared signals then the unused signals are TDM0RCLK, TDM1RCLK, TDM0TDAT, TDM1TDAT, TDM1TCLK, and TDM1TSYN. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-39...
Page 976 The TDM does not (RDATA_A) data share signals with (TDATA_A) others TDM modules. Receive and transmit share sync and clock signals. One active data link. direction input Output Inout Input MSC8144E Reference Manual, Rev. 3 19-40 Freescale Semiconductor...
Page 977 The TDM does not DATA_A DATA_B share signals with other TDM modules. Receive and transmit share the sync, clock, and data signals. Two full duplex active data links. direction Inout Inout Inout Input 1110 Reserved MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-41...
Page 978 (TDATA_A) and frame clock with other TDM modules. Receive and transmit shared sync and clock signals. One active data link. direction input Output Inout Input MSC8144E Reference Manual, Rev. 3 19-42 Freescale Semiconductor...
Page 979 TDM modules. Receive and transmit share the sync, clock, and data signals. Two full duplex active data links. direction Inout Inout Inout Input 1110 Reserved MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-43...
Page 980: Tdmx Receive Interface Register (Tdmxrir)
Receive First Threshold Level Receive first threshold interrupt is Determines whether the receive first threshold interrupt is pulse. pulse or level. For details, see Section 19.2.6.3. Receive first threshold interrupt is level. MSC8144E Reference Manual, Rev. 3 19-44 Freescale Semiconductor...
Page 981 For examples, see Section 19.2.4.2. stored as the most significant bit in the internal memory. The first bit of a received channel is stored as the least significant bit in the internal memory MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-45...
Page 982: Tdmx Transmit Interface Register (Tdmxtir)
Transmit First Threshold Level Transmit first threshold interrupt is pulse. Determines whether the Transmit first threshold Transmit first threshold interrupt is level. interrupt is pulse or level. For details, see Section 19.2.6.3. MSC8144E Reference Manual, Rev. 3 19-46 Freescale Semiconductor...
Page 983 The least significant bit of the memory is sent out at the first transmit data bit. Table 19-12. Transmit Data Delay for Transmit Frame Sync Frame Sync Delay Frame Sync Edge Data Edge Transmit Clocks –1 –0.5 –0.5 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-47...
Page 984: Tdmx Receive Frame Parameters (Tdmxrfp)
The field value is negative because the data is driven out before the transmit frame sync sample. 19.7.1.4 TDMx Receive Frame Parameters (TDMxRFP) TDMxRFP TDMx Receive Frame Parameters Offset 0x3FE0 — RNCF Type Reset — RCDBL — RT1 RUBM Type Reset MSC8144E Reference Manual, Rev. 3 19-48 Freescale Semiconductor...
Page 985 Section 19.2.6. 0010 Reserved. 0011 The receiver channel size is 4 bits. 0100– 0110 Reserved. 0111 Receiver channel size is 8 bits. 1000– 1110 Reserved. 1111 Receiver channel size is 16 bits. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-49...
Page 986 The total number of channels must have a granularity of two. xxxxxx11 The total number of channels must have a granularity of four. Reserved. xxxxx111 The total number of channels must have a granularity of eight. MSC8144E Reference Manual, Rev. 3 19-50 Freescale Semiconductor...
Page 987: Tdmx Transmit Frame Parameters (Tdmxtfp)
Table 19-16 describes the TNCF valid value as a function of the TDMxGIR[RTSAL] field (Receive and Transmit Sharing and Active Links). For details, see Section 19.2.5. — Reserved. Write to zero for future compatibility. 15–11 MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-51...
Page 988 All the channels are read from transmit channels are located in TDMxTCPR0. For details, the same data buffer in the see Section 19.2.6.4. internal MBus. Note: When this bit is set, the TDMxTIR[TRDO] bit should be cleared. MSC8144E Reference Manual, Rev. 3 19-52 Freescale Semiconductor...
Page 989: Data Buffer Size And A/M-Law Channels
1. The buffer size is aligned to 8 bytes, so bits 0–2 must be set to “111”. For details, see Section 19.2.6.1, Data Buffer Size and A/m-law Channels, on page 19-23. Note: The minimum buffer size is 16 bytes. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-53...
Page 990: Tdmx Transmit Data Buffer Size (Tdmxtdbs)
The actual address of each receive data buffer is RCDBA + (RGBA << 16). See Section 19.2.6.2. Table 19-19. TDMxRGBA Bit Descriptions Name Reset Description — Reserved. Write to zero for future compatibility. 31–16 MSC8144E Reference Manual, Rev. 3 19-54 Freescale Semiconductor...
Page 991: Tdmx Transmit Global Base Address
Determines the global base address of the transmit data buffers. It is added to channel data buffer address and to the current transmit displacement to generate the actual address. 19.7.1.10 TDMx Transmit Force Register (TDMxTFR) TDMxTFR TDMx Transmit Force Register 0x3F10 — Type Reset Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-55...
Page 992: Tdmx Receive Force Register (Tdmxrfr)
TDMxRFPx[RCDBL]. If TDMxRFP[RCDBL] = 0x000, achieve the maximum value by setting PUV = TDMxRFP[RNCF]. If TDMxRFP[RCDBL] is not 0x000, set the PUV using PUV = 64/TDMxRFP[RCS] × RNBx[RNB]. See page 19-48 for TDMxRFP details and page 19-68 for TDMxRNB details. MSC8144E Reference Manual, Rev. 3 19-56 Freescale Semiconductor...
Page 993: Tdmx Parity Control Register (Tdmxpcr)
Parity interrupt is level-triggered. 19.7.2 Control Registers The following sections describe the TDM control registers. 19.7.2.1 TDMx Adaptation Control Register TDMxACR TDMx Adaptation Control Register Offset 0x3FB0 — Type Reset — Type Reset MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-57...
Page 994: Tdmx Receive Control Register
Reserved. Write to zero for future compatibility. 31–1 Receive Enable Receiver is disabled. Determines whether the receive TDM is enabled or disabled. Receiver is enabled. Note: Setting this bit is the last step in initializing the receiver. MSC8144E Reference Manual, Rev. 3 19-58 Freescale Semiconductor...
Page 995: Tdmx Transmit Control Register (Tdmxtcr)
(TDMxRDBFT) + 8—the RFTE bit in the TDMx Receive Event Register (TDMx RER) is set. If the associated enable bit is also set, an interrupt is generated. This register can be updated at any time, even when the TDMx receiver is enabled. For details, see Section 19.2.6.3. MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-59...
Page 996: Tdmx Transmit Data Buffer First Threshold
0x000000 to (TDBS – 7) 23–0 Determines the location of the first threshold in the transmit data buffers. The register value has a granularity of eight bytes; that is, the three LSBits are always clear. MSC8144E Reference Manual, Rev. 3 19-60 Freescale Semiconductor...
Page 997: Tdmx Receive Data Buffer Second Threshold
Transmit Data Buffers Displacement Register (TDMxTDBDR) = the Transmit Data Buffers Second Threshold (TDMxTDBST) + 8—then the TSTE bit in the TDMx Transmit Register (TDMxTER) is set. If MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-61...
Page 998: Tdmx Receive Channel Parameter Register N
TDMxPCR on page 19-57). Table 19-32. TDMxRCPRn Bit Descriptions Name Reset Description Settings RACT — Receive Channel Active The channel is non-active. Set when the receive channel n is active. The channel is active. MSC8144E Reference Manual, Rev. 3 19-62 Freescale Semiconductor...
Page 999: Tdmx Transmit Channel Parameter Register N
Note: All TDMxTCPRn with an index number (n) less than or equal to the TDMxTFP[TNCF] bit (see page 19-51) should be valid when setting the corresponding TDMxTCR[TEN] bit (see page 19-59). MSC8144E Reference Manual, Rev. 3 Freescale Semiconductor 19-63...
Page 1000: Tdmx Receive Interrupt Enable Register (Tdmxrier)
Receive Sync Error Event Enable Receive sync error is masked. Enable assertion of the receive error interrupt when the Receive sync error is enabled. Receive Sync Error (RSE) bit is set (see page 19-69). MSC8144E Reference Manual, Rev. 3 19-64 Freescale Semiconductor...

Freescale Semiconductor MSC8144E Reference Manual

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Chip-Level Arbitration and Switching System (CLASS)

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