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Boot Program
11.
The EEPROM slaves can have
However, there must be external logic that performs the actions that the master performs
during its boot sequence. The logic may be implemented as periodic polling by the
master, asserting
If there is a shared EEPROM in use in any stage of the reset/boot flow (RCW, serial
12.
RapidIO interface configuration, MAC address, I
RCW from the shared EEPROM.
Note:
If the reset master (RCWHR[RM]) fails (due to a stuck SDA) to read the data at 0x11
or 0x8F of the EEPROM or fails during the sequence of driving the RCW to the reset
slaves, the core goes into a debug state and writes the appropriate error code to the M2
memory (see Section 6.8).
6.4.2 Example Configuration
Figure 6-2 describes a I
MSC8122 #1 is a reset slave. The reset master uses {GPIO[0–3], GPIO[21]} to release the reset
slaves. The MSC8144 boot supports up to 15 slaves on a single EEPROM (for RCW). There are
two possibilities as to how the reset slave STOP_BS signals are handled:
If there are 5 slaves or less, connect each GPIO line directly to one of the slaves. The
master deasserts and asserts the lines when necessary.
If there are more than 5 slaves, GPIO[21] is used to latch the values of GPIO[0–3] into the
decoder glue logic (latch when high). This value indicates which of the slave STOP_BS
signals to pull low. When an all 1 values are latched, all STOP_BS signals should be
pulled high.
6-6
HRESET
to the reset master, or using an FPGA or other implementation)
NMI
2
C multi device system in which MSC8122 #0 is a reset master and
MSC8144E Reference Manual, Rev. 3
/
asserted without the master being reset.
SRESET
2
C boot), all devices MUST load their
Freescale Semiconductor
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