Pin Data Register (Pdat) - Freescale Semiconductor MSC8144E Reference Manual

GPIO

22.5.2 Pin Data Register (PDAT)

PDAT
Bit 31 30 29
D31 D30 D29
Type
Reset 0 0 0
Bit 15 14 13
D15 D14 D13
Type
Reset 0 0 0
A read of a PDAT register returns the data at the pin, independently of whether the port is defined
as an input or output. Thus, output conflicts at the pin can be detected by comparing the written
data with the data on the pin. A write to the PDATx is sampled in a register bit, and if the
equivalent PDIR bit is configured as an output, the value sampled for that bit is driven onto its
respective pin. PDAT can be read or written at any time.
If a pin is selected as GPIO, it is accessed through the PDAT. Data written to the PDAT register
is stored in an output register. If a port is configured as an output, the output register data is gated
onto the pin. When PDAT is read, the GPIO pin itself is read. If a GPIO port is configured as an
input, data written to the PDAT register is still stored in the output register, but it is prevented
from reaching the actual pin. When the PDAT register is read, the state of the actual pin is read.
When a GPIO port has Ethernet functionality (see Table 22-1), data written to PDATx is stored
in the output register, but it is prevented from reaching the external port. Read of PDATx returns
the data at the external port, independently of whether the port is defined as input or output in
Ethernet Controller.
22-8
Pin Data Register
28 27 26 25
D28 D27 D26 D25
0 0 0 0
12 11 10 9
D12 D11 D10 D9
0 0 0 0
MSC8144E Reference Manual, Rev. 3
24 23 22 21
D24 D23 D22 D21
R/W
0 0 0 0
8 7 6 5
D8 D7 D6 D5
R/W
0 0 0 0
Offset 0x08
20 19 18 17
D20 D19 D18 D17
0 0 0 0
4 3 2 1
D4 D3 D2 D1
0 0 0 0
Freescale Semiconductor
16
D16
0
0
D0
0