Reset Configuration Word High Register (Rcwhr) - Freescale Semiconductor MSC8144E Reference Manual

5.3.2 Reset Configuration Word High Register (RCWHR)

RCWHR
Bit 31 30 29
— RM EWDT
Type
Reset Value depends on the reset configuration word high loaded during reset flow.
Bit 15 14 13
PTE —
Type
Reset Value depends on the reset configuration word high loaded during reset flow.
The RCWHR is a read-only register that derives its values from the reset configuration word high
loaded during the reset flow. Table 5-9 defines the RCWHR bit fields.
Name
— Reserved. Write to zero for future compatibility.
31
RM Reset Initiator Configure Targets
30 This bit must be set for single MSC8144E device
loading of the RCW from an I
2
BPRT is I C. See Chapter 6, Boot Program. The
number of reset targets is defined externally.
EWDT Enable Watchdog Timer
29 Selects the status of the software watchdog when
coming out of reset. The user can override this
value by writing a 1 to the System Watchdog
Control Register (SWCRR[SWEN]) during system
initialization.
BPRT Boot Port Select
28–23 Defines the boot port interface configuration.
— Reserved. Write to one for future compatibility.
22
RIO RapidIO Host Access Enable
21 Enables RapidIO access to internal memory after
boot.
PTE RapidIO Prescale Timer Enable
20–15 Compute the value using:
(OCeaN clock/8 MHz) –1, rounded to the nearest
whole value.
— Reserved. Write to zero for future compatibility.
14
PIN_MUX1 Pin Multiplexing
13–10 Stores the value of the signals sampled during
reset. This selects the I/O multiplexing mode.
DEVID Device ID
9–4 Stores the value of the signals sampled during
reset.
Freescale Semiconductor
Reset Configuration Word High Register
28 27 26 25
BPRT
12 11 10 9
PIN_MUX
Table 5-9. RCWHR Bit Descriptions
Description
2
C EEPROM and
MSC8144E Reference Manual, Rev. 3
24 23 22 21
— RIO
R
8 7 6 5
DEVID
R
0 Reset target.
1 Reset initiator.
0 Watchdog timer initially disabled.
1 Watchdog timer initially enabled.
See Table 5-10.
0 RapidIO access to internal memory disabled.
1 RapidIO access to internal memory enabled.
See Chapter 3 External Signals.
00000 Initiator device/Device 0.
00001–
11111 Target device number (from 1 to 31).
Reset Programming Model
Offset 0x04
20 19 18 17
PTE
4 3 2 1
ER SLP CTLS
Settings
16
0
5-19