Port 0 Implementation Error Command And Status Register (P0Iecsr) - Freescale Semiconductor MSC8144E Reference Manual

16.6.46 Port 0 Implementation Error Command and Status Register
(P0IECSR)
P0IECSR Port 0 Implementation Error Command and Status Register
Bit 31 30 29
RETE
TYPE W1C
RESET 0 0 0
Bit 15 14 13
TYPE
RESET 0 0 0
P0IECSR contains status bits that are asserted when an implementation-defined error occurs.
Bit Reset
RETE 0
31
— 0
30–0
Freescale Semiconductor
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
Table 16-88. P0IECSR Field Descriptions
Retry Error Threshold Exceeded
Set when the number of consecutive retries reaches the retry error threshold in the Physical
Retry Error Threshold Configuration Register (PRETCR). RETE is cleared by writing a value of 1
to it. This bit is set again if another retry is received and the number of consecutive retries
continues to exceed the retry error threshold.
Reserved. Write to zero for future compatibility.
MSC8144E Reference Manual, Rev. 3
24 23 22 21
—
R
0 0 0 0
8 7 6 5
—
R
0 0 0 0
Description
RapidIO Programming Model
Offset 0x10130
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
16
0
0
0
16-153