L2 Icache Lrm State Register (L2Ic_Lrm) - Freescale Semiconductor MSC8144E Reference Manual

Table 11-8. L2IC_CR2 Bit Descriptions (Continued)
Name Reset
CGL 0 Cache Global Lock
1 Indicates whether cache is in global lock mode or
not. Assertion of global lock mode is ignored during
a cache sweep operation.
CE 0
0 Indicates whether the two L2 cache memory
modules are enabled or disabled. At reset
deassertion, the two modules are disabled. Once
the cache memory is enabled. it may be disabled
only by reset. In disable mode the clock inside each
memory module is disabled and power is saved.
Note:

11.8.4 L2 ICache LRM State Register (L2IC_LRM)

L2IC_LRM
Bit 31 30 29
—
Type
Reset 0 0 0
Bit 15 14 13
—
Type
Reset 0 0 0
This register holds the state of the Line Replacement Mechanism (LRM) of the cache, which is
PLRU in this implementation. The PLRUB[3–0] fields hold the PLRU state of the cache lines
pointed to by the debug counter. There are seven PLRU bits for each index in the cache to
determine the line to be replaced. The PLRU bits are updated when a new line is allocated or
replaced and when there is a line hit. A line is selected for replacement according to the PLRU bit
encoding shown in Table 11-10 (initial values of B[6–0] is all zeros). This register is read only,
accessible only in L2 ICache debug mode. Table 11-9 defines the L2IC_LRM bit fields.
Name Reset
— 0 Reserved. Write to zero for future compatibility.
31
PLRUB3 0 PLRU Bits 3
Holds the state bits for indexes (4 × i) + 3 (i is an
30–24
integer).
— 0 Reserved. Write to zero for future compatibility.
23
PLRUB2 0 PLRU Bits 2
Holds the state] bits for indexes (4 × i) + 2 (i is an
22–16
integer).
Freescale Semiconductor
Description
Cache Memory Enabled
This is a sticky bit.
L2 ICache LRM State Register
28 27 26 25
PLRUB3
0 0 0 0
12 11 10 9
PLRUB1
0 0 0 0
Table 11-9. L2IC_LRM Bit Descriptions
Description
MSC8144E Reference Manual, Rev. 3
0 Cache global lock mode not active.
1 Cache global lock mode active.
0 Cache memory disabled.
1 Cache memory enabled.
24 23 22 21
—
R
0 0 0 0
8 7 6 5
—
R
0 0 0 0
0 Cache line not valid.
1 Cache line valid.
0 Cache line not valid.
1 Cache line valid.
Programming Model
Settings
Offset 0x0C
20 19 18 17
PLRUB2
0 0 0 0
4 3 2 1
PLRUB0
0 0 0 0
Settings
16
0
0
0
11-29