Dma Channel Active Status Register (Dmachastr) - Freescale Semiconductor MSC8144E Reference Manual

14.6.19 DMA Channel Active Status Register (DMACHASTR)

DMACHASTR
Bit 31 30 29
Type
Reset 0 0 0
Bit 15 14 13
A15 A14 A13 A12
Type
Reset 0 0 0
Each bit in the DMACHASTR corresponds to the active status of the associated channel. If set, a
bit associated with a channel indicates that the channel is still active. A channel can stay active
even after DMACHCR[ACTV] is cleared or DMACHDR[DISx] is set. A DMACHASTR bit is
reset only when its corresponding channel completes the shutdown procedure.
14.6.20 DMA Channel Freeze Status Register (DMACHFSTR)
DMACHFSTR
Bit 31 30 29
D15 S15 D14 S14
Type
Reset 0 0 0
Bit 15 14 13
D7 S7 D6
Type
Reset 0 0 0
Each bit in the DMACHFSTR corresponds to the freeze status of the associated channel. If set, a
bit associated with a channel indicates that the channel is still frozen.
Note: The corresponding bits are cleared when a channel is activated.
Freescale Semiconductor
DMA Channel Active Status Register
28 27 26 25
0 0 0 0
12 11 10 9
A11 A10 A9
0 0 0 0
DMA Channel Freeze Status Register
28 27 26 25
D13 S13 D12
0 0 0 0
12 11 10 9
S6 D5 S5 D4
0 0 0 0
MSC8144E Reference Manual, Rev. 3
24 23 22 21
—
R
0 0 0 0
8 7 6 5
A8 A7 A6 A5
R
0 0 0 0
24 23 22 21
S12 D11 S11 D10
R
0 0 0 0
8 7 6 5
S4 D3 S3 D2
R
0 0 0 0
DMA Programming Model
Offset 0x380
20 19 18 17
0 0 0 0
4 3 2 1
A4 A3 A2 A1
0 0 0 0
Offset 0x388
20 19 18 17
S10 D9 S9 D8
0 0 0 0
4 3 2 1
S2 D1 S1 D0
0 0 0 0
16
0
0
A0
0
16
S8
0
0
S0
0
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