Pci Outbound Address Translation - Freescale Semiconductor MSC8144E Reference Manual

PCI
The translation windows are disabled after reset, that is, after reset, the VCOP acknowledges, by
asserting , only externally initiated transactions toward the PIMMR window on the
PCI_DEVSEL
PCI bus. Other transactions are not acknowledged until the inbound translation windows are
enabled.
PCI Memory View
0
PCI inbound
base
address
PCI inbound
window size
4G
Figure 15-7. Inbound PCI Memory Address Translation

15.1.8.6 PCI Outbound Address Translation

Transactions to the PCI Outbound Window (0xE0000000 to 0xE7FFFFFF in the local memory
space) are forwarded to the PCI Configuration Access Registers or to the PCI port. If the address
matches the PCI Configuration Access Registers memory space (0xE7FFFFFF0 to 0xE7FFFFFF
in the local memory area), the transaction is forwarded to one of the PCI Configuration Access
Registers. Otherwise, if the address hits any of the outbound translation windows, the transaction
is forwarded to PCI port.
Note: Do not attempt to access the PCI Outbound Window until the PCICCR[BMST] bit is
set. See Section 15.2.2.3, PCI Command Configuration Register (PCICCR), on page
15-23 for details about the BMST bit.
Outbound address translation is provided to allow the outbound transactions to access any
address over the PCI memory or I/O space. Translation window base addresses are defined in the
PCI outbound base address registers. See page 15-44 for details. Transactions to these address
ranges are issued on the PCI bus with a translated address. The translation addresses are defined
15-16
System memory
Inbound address
translation
PCI memory
Peripheral
memory
MSC8144E Reference Manual, Rev. 3
Internal Memory View
0
Peripheral memory
window
Local memory
PCI memory
4G
Freescale Semiconductor
PCI inbound
translation
address
PCI inbound
window size