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PE
PT
SBR[12–0]
Baud-Rate
CLASS64 clock
Generator
TDRE Interrupt Source
TC Interrupt Source
20.1.1 Character Transmission
To transmit data, one of the SC3400 cores or an external host writes the data character to the SCI
Data Register (SCIDR), which is then transferred to the transmitter shift register. The transmitter
shift register then shifts out the data bits on the
and appends them with a stop bit. The SCI data register is the write-only buffer between the
MBus and the transmit shift register.
The UART also sets a flag, the transmit data register empty flag (TDRE), every time it transfers
data from the buffer (SCIDR) to the transmitter shift register. If the Transmit Interrupt Enable
(TIE) bit in the SCICR is set, the TDRE flag asserts a UART interrupt request. The transmit
interrupt service routine responds to this flag by writing another character to the transmitter
buffer (SCIDR), while the shift register is still shifting out the first character. If the TDRE flag is
set and no new data or break character transferred to the shift register, the UART sets a flag,
transmit complete (TC) and
Freescale Semiconductor
SCI Data Register T[7–0]
11-Bit Transmit Shift Register
H 8 7 6 5 4 3 2 1 0 L
M
T8
Parity
Generation
³ 16
TDRE
TIE
TC
TCIE
Figure 20-6. Transmitter Block Diagram
becomes idle.
UTXD
MSC8144E Reference Manual, Rev. 3
MBus
Transmitter Control
TE
SBK
signal, after it prefaces them with a start bit
UTXD
Transmitter
UTXD
Loop
To
Control
Receiver
LOOPS
RSRC
20-7
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