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10.4
Data Channel and Write Queue
The Data Channel comprises the:
Data cache (DCache)
Data fetch unit (DFU)
Data control unit (DCU)
Write-back buffer (WBB)
Data write buffer (DWB)
This channel is a two-way channel for reading and writing information from the core to/from
higher level memory (M2 or L2) and Control Memory (internal blocks and external peripherals)
spaces. The DCache, which operates at core speed, keeps the recently accessed data. Whenever
addressed data (from a cacheable memory area) is found in the array, it is immediately made
available to the core (DCache hit) in a read, and updated if written to. When the required address
is not found in the array, a DCache miss occurs, and the data is loaded to the DCache from the
external (off-platform) memory by the DFU, and driven to the core. The DFU operates in parallel
with the core and implements a pre-fetch algorithm to load to the DCache. Because there is a high
probability that the information will be needed again, the loading of the data can reduce the
number of data cache misses. The channel differentiates between cacheable and non-cacheable
addresses. For cacheable addresses, it supports the write-back allocate writing policy. The
selection is made on an address segment basis, as programmed in the MMU. The Data Channel
supports the arrangement of data in both big- and little-endian formats. Core data types can be
byte, word, long (4 byte) or 2 long (8 byte) wide. The data channel has the following features:
32 KB
8 ways with 16 lines per way
Capable of serving two data accesses in parallel (Xa, Xb)
Multi-task support
Real-time support through locking flexible boundaries
Software coherency support
Write-back writing policy
Pre-fetch capability
Note:
See the MSC8144 SC3400 DSP Core Subsystem Reference Manual for details on the
Data Channel and the L1 DCache.
Freescale Semiconductor
MSC8144E Reference Manual, Rev. 3
Data Channel and Write Queue
10-5
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