Pci Protocol Fundamentals - Freescale Semiconductor MSC8144E Reference Manual

PCI

15.1.3 PCI Protocol Fundamentals

The bus transfer mechanism on the PCI bus is called a burst. A burst is comprised of an address
phase and one or more data phases. All signals are sampled on the rising edge of the PCI clock.
Each signal has a setup and hold window with respect to the rising clock edge, in which
transitions are not allowed. Outside this aperture, signal values or transitions have no
significance. PCI data transfers are controlled by the following three fundamental signals:
is driven by an initiator to indicate the beginning and end of a transaction.
PCI_FRAME
(initiator ready) is driven by an initiator, allowing it to force wait cycles.
PCI_IRDY
(target ready) is driven by a target, allowing it to force wait cycles.
PCI_TRDY
The bus is idle when both
is asserted indicates the beginning of the address phase. The address and the bus
PCI_FRAME
command code are transferred in that cycle. The next cycle ends the address phase and begins the
data phase.
During the data phase, data is transferred in each cycle that both
asserted. Once the VCOP, as an initiator, has asserted
until the current data phase completes, regardless of the state of
PCI_FRAME
VCOP, as a target, has asserted
or until the current data phase completes.
PCI_STOP
When the VCOP (as an initiator) intends to complete only one more data transfer,
deasserted and
PCI_IRDY
target indicates it is ready (
15.1.4 Addressing
The PCI specification defines three physical address spaces—memory, I/O, and configuration.
The memory and I/O address spaces are standard for all systems. The configuration address space
has been defined specifically to support PCI hardware configuration. Each PCI device decodes
the address for each PCI transaction with each agent responsible for its own address decode. The
information contained in the two lower address bits (AD1 and AD0) depends on the address
space. In the I/O address space, all 32 address/data lines provide the full byte address.
used for the generation of
transfer. In the configuration address space, accesses are decoded to a 4-byte address using
. An agent determines if it is the target of the access when a configuration command is
AD[7–2]
decoded, is asserted, and
IDSEL
transaction.
For memory accesses, the address is decoded using
incremented internally by 4 bytes until the end of the burst transfer. Another initiator in a
memory access should drive 0b00 on
15-4
and
PCI_FRAME PCI_IRDY
or
PCI_TRDY PCI_STOP
is asserted (or kept asserted) indicating the initiator is ready. After the
asserted) the bus returns to the idle state.
PCI_TRDY
and indicate the least significant valid byte involved in the
PCI_DEVSEL
are 0b00; otherwise, the agent ignores the current
AD[1–0]
during the address phase to indicate a linear
AD[1–0]
MSC8144E Reference Manual, Rev. 3
are deasserted. The first clock cycle in which
PCI_IRDY
, it does not change
PCI_IRDY
it does not change
PCI_DEVSEL
; thereafter, the address is
AD[31–2]
and are
PCI_TRDY
or
PCI_IRDY
. Once the
PCI_TRDY
, ,
PCI_TRDY
is
PCI_FRAME
are
AD[1–0]
Freescale Semiconductor