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2
I
C
2
24.5.5 I
C Data Register (I2CDR)
I2CDR
Bit
7
6
Type
Reset
0
Table 24-5 describes the I2CDR fields.
Name
Reset
DATA
0
Data
7–0
Transmission starts when an address and the R/W bit are written to the data register and the I
interface performs as the initiator. A data transfer is initiated when data is written to the I2CDR.
The most significant bit is sent first in both cases. In the initiator receive mode, reading the data
register allows the read to occur, but also allows the I
on the I
24.5.6 Digital Filter Sampling Rate Register (I2CDFSRR)
I2CDFSRR
Bit
7
6
—
Type
Reset
0
Table 24-6 describes the I2CDFSRR fields.
Name
Reset
—
0
Reserved. Write to zero for future compatibility.
7–6
DFSR
010000
Digital Filter Sampling Rate
5–0
To assist in filtering out signal noise, the sample rate is programmed. This field is used to prescale
the frequency at which the digital filter takes samples from the I
rate is calculated by dividing the system frequency by the non-zero value of DFSR. If I2CDFSRR
is set to zero, the I
should be defined by the system noise and the I2CFDR[FDR] value. DFSR must be less than six
times the division factor defined by I2CFDR[FDR].
24-20
2
I
C Data Register
5
0
0
Table 24-5. I2CDR Bit Descriptions
2
C interface. In target mode, the same function is available after it is addressed.
Digital Filter Sampling Rate Register
5
0
0
Table 24-6. I2CDFSRR Bit Descriptions
2
C bus sample points default to the reset divisor 0x10. The value of DFSR
MSC8144E Reference Manual, Rev. 3
4
3
DATA
R/W
0
0
Description
2
C module to receive the next byte of data
4
3
DFSR
R/W
1
0
Description
Offset 0x10
2
1
0
0
Offset 0x14
2
1
0
0
2
C bus. The resulting sampling
Freescale Semiconductor
0
0
2
C
0
0
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